摘要
本文提出了ＭＰＥＧ２视频解码器主要功能模块的专用ＶＬＳＩ结构．其中包括一种新的适用于ＭＰＥＧ２标准的ＩＤＣＴ实现方法，对于８点一维ＩＤＣＴ，只用７个变量乘常系数乘法器和１０个加／减法器，在４个时钟周期内能处理完８点数据；通过合理分配画面存储结构，提出了一种新的流水线的运动补偿预测结构．用ＶＨＤＬ语言进行仿真，并用１．０μｍＣＭＯＳ单元库进行综合。
Abstract VLSI architecture of special functional block units for MPEG2 video decoder is proposed. A novel realization methodology of IDCT compatible with MPEG2 is presented, for 1 D IDCT, it takes 4 clocks to process 8 point data by using only 7 variables multiplying constant coefficients multipliers and 10 adders/subtracters. A novel pipeline VLSI structure of motion compensation prediction is designed by allocating suitable picture storage structure. The design is simulated by VHDL and synthesized by 1.0μm CMOS cells library, and it can be used in MPEG2 MP@ML video decoder.
