摘要
使用化学机械抛光(CMP)的方式,对商用芯片进行拆解,获得了不同制造工艺的铜/低k介质互连结构样品。通过对所获得的32 nm制造工艺的铜/低k介质互连结构样品进行进一步的化学机械抛光实验来研究抛光过程中出现的损伤。实验结果发现,抛光压力过大和过小分别会造成宏观缺陷和导线腐蚀,互连线的分布会导致导线自身的碟型缺陷、不同图案布线结构交界两侧明显的表面高度差异以及同一图案布线结构内部的表面周期性高度起伏。这种表面高度差异可以通过预补偿的方式得到一定的改善。
Some commercial CPU chips were disassembled with the chemical mechanical polishing（CMP） method to achieve Cu/low-k interconnect structures with different manufacturing techniques. The Cu/low-k interconnect structures with manufacturing technique of 32 nm were polished further to study the damages occured in the chemical mechanical polishing process. The results show that the larger and smaller polishing pressures lead to the macroscopic defects and wire erosions separately. In addition, wiring pattern distribution would result in the dishing effects of wires, the obvious difference in surface height at the sides of different wiring pattern joints and the surface height changing in periods of the same wiring pattern, this surface height difference would be improved with the pre-offset method.
出处
《电子元件与材料》
CAS
CSCD
北大核心
2014年第7期60-65,共6页
Electronic Components And Materials
基金
"973"计划资助项目(No.2011CB013102)
国家自然科学基金资助项目(No.91223202
No.51375255)
国际科技合作项目资助(No.2011DFA70980)
