摘要
给出了漂移区为线性掺杂的高压薄膜SOI器件的设计原理和方法 .在Si膜厚度为 0 15 μm、隐埋氧化层厚度为 2 μm的SOI硅片上进行了LDMOS晶体管的制作 .首次对薄膜SOI功率器件的击穿电压与线性掺杂漂移区的杂质浓度梯度的关系进行了实验研究 .通过对漂移区掺杂剂量的优化 ,所制成的漂移区长度为 5 0 μm的LDMOS晶体管呈现了高达 6 12V的击穿电压 .
Principle and method for designing high voltage thin film SOI devices with linearly doped drift region are given. LDMOS transistors are fabricated on the SOI wafers with Si film of 0.15μm and buried oxide of 2μm. The dependence of breakdown voltages of the thin film SOI devices on the concentration gradient in the linearly doped drift region is experimentally investigated. Based on the optimization of the impurity dose in drift region, the breakdown voltage over 612 V is observed in the SOI LDMOS transistors with 50μm drift region.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2001年第2期164-167,共4页
Acta Electronica Sinica
关键词
薄膜SOI
半导体器件
线性掺杂
漂移区
Calculations
Electric breakdown
Electric potential
Optimization
Thin films
VLSI circuits
