摘要
该文主要介绍了一个应用于12bit SAR ADC中的高精度比较器。基于预放大锁存理论,完成了预放大级、锁存比较级和输出缓冲级三个模块的设计。为达到所需比较器的精度,对预放大级进行优化设计,锁存比较级电路采用的是动态锁存结构,而输出缓冲级采用的是SR锁存电路。该比较器是在GSMC 0.18μm工艺下完成仿真设计的,经测试,在300M时钟下,比较器的分辨率为39μV。
This paper is mainly aimed at a high-resolution comparator in a 12bit SAR ADC.Based on the pre-amplifier latch theory,the main modules of comparator are preamplifier,latch comparator and output stage.To meet the design requirements,we optimize the pre-amplifier,adopt a dynamic latch structure for the latch comparative stage,and choose the SR latch for the output stage.All the conclusions are simulated with GSMC 0.18 μ m process model,after testing,when the clock frequency at 300MHz,the resolution of the comparator achieved 39 μ V.
出处
《电子质量》
2013年第8期24-27,共4页
Electronics Quality
关键词
比较器
预放大锁存
高精度
： Comparator
Pre-amplifier latch
High-resolution
