摘要
基于预放大锁存快速比较理论,提出了一种高速高精度CMOS比较器的电路拓扑.该比较器采用负载管并联负电阻的方式提高预放大器增益,以降低失调电压.采用预设静态电流的方式提高再生锁存级的再生能力,以提高比较器的速度.在TSMC0.18μm工艺模型下,采用Cadence Specture进行仿真.结果表明,该比较器在时钟频率为1GHz时,分辨率可以达到0.6mV,传输延迟时间为320ps,功耗为1mW.
Base on the analysis of preamplifier latch comparator,there is a high speed high resolution CMOS comparator presented.The comparator uses negative resistors in parallel with load transistors to improve the gain of preamplifier,in order to reduce offset voltage.Meanwhile,the comparator uses a preset quiescent current to improve the regenerative speed.Fabricated in TSMC 0.18 μm process model,it is simulated with Cadence specture.The simulated results show the clock could be as high as 1GSPS,the resolution is 0.6 mV,delay time is 320 ps,and power consumption is 1 mW.
出处
《微电子学与计算机》
CSCD
北大核心
2011年第1期50-53,共4页
Microelectronics & Computer
关键词
高速比较器
低失调比较器
失调电压
预放大锁存比较器
high speed comparator
low offset comparator
offset voltage
pre-amplifier latch comparator
