摘要
介绍了一种用于封装万门至十万门级 CMOS门阵列电路的 PCA1 32多层陶瓷外壳的研制。该外壳的设计采用了 CAD设计布线 ,模拟并优化外壳的信号线电阻、线间电容、电感及传输延迟等参数 ,使其满足电路要求。并且通过结构可靠性设计 ,使外壳抗机械冲击、温度冲击能力大大提高 ,满足了高可靠应用要求。
A multi-layer ceramic package has been developed for 10k to 10 0k CMOS gate array circuits.The package is designed with CAD technology.Paramete rs including signal line resistance,line -to-line capacitance,inductance and sign al transmission delay are simulated and optimized.In the meantime,the structura l design for reliability is made,which e nhances the resistance of the package to mechanical strike and thermal shock.Fin ally,the process flow is described and t he results are discussed
出处
《微电子学》
CAS
CSCD
北大核心
2000年第3期206-208,共3页
Microelectronics
关键词
封装
CMOS电路
门阵列
外壳
CMOS
Gate arra y
Package
Multi-layer ceramic package
