摘要
环路滤波器是鉴相法测量相位噪声系统中决定相位噪声提取性能的重要部件,采用数字实现方法时,测量系统分析带宽和锁相环路工作要求决定了该滤波器为极窄带宽滤波器。针对高性能极窄带宽的设计要求,通过理论分析,提出了适用于相位噪声测量系统的分级多相抽取数字滤波器结构。该结构采用了多级抽取、多相结构、存储器优化、乘法器优化等改进方法。论文中对优化后的滤波器结构与现有滤波器实现结构分别在FPGA中进行实现。通过比较两者实验结果,给出的极窄带宽滤波器分级多相实现结构在达到系统指标要求的条件下,占用资源为传统结构的33.8%,计算量为传统结构的54.5%。
The loop filter is a key component in phase noise test systems, which determines the performance of phase noise extraction. The filter built by digital method is an ultra-narrow-band filter. This paper presents a structure of polyphase decimation filter which is suitable for phase noise measurement system according to the design requirements of high performance and ultra-narrow-band filters. The structure of the filter is improved by multistage decimation, polyphase structure, memory optimization and multiplier optimization. The improved filter and typical filter are built in FPGA re- spectively. A comparison of the experimental results of the two filters shows that the improved filter requires only 33.8% FPGA resource and 54.5% computational complexity of the typical filter while meeting all system requirements.
出处
《电子测量与仪器学报》
CSCD
2012年第11期933-938,共6页
Journal of Electronic Measurement and Instrumentation
基金
中央高校基本科研业务费专项资金(编号:K50510040011
K50511040009)资助项目
关键词
相位噪声测量
环路滤波器
多相结构
phase noise measurement
loop filter
polyphase structure
