摘要
编写Verilog程序对32×32高性能乘法器的结构算法进行验证.为提高乘法器的性能,采用CSA和4-2压缩器相结合的改进Wallace树结构进行部分积压缩;采用速度快、面积小的传输门逻辑设计Booth2编码电路和压缩电路;运用欧拉路径法设计优化部分积产生电路;采用基4 Kogge-Stone树算法基于启发式欧拉路径法设计优化64位超前进位加法器.该乘法器全定制设计采用SMIC0.18μm 1P4M CMOS工艺,版图面积0.179 41mm2,在大量测试码中最坏情况完成一次乘法运算时间为3.252 ns.
The structure and the algorithm of a 32 × 32 high performance multiplier are validated by simulation using Verilog in this .paper. In order to improve performance of multiplier, the improved structure of Wallace tree, which combines the carry save accumulator adder and the 4 2 compres sor, is used in partial product compressor circuit. The transmission gate logic circuits, a high speed and small area technique for VLSI applications, have been successfully adopted in Booth2 coding cir cuit and compression circuit. Euler path method is employed to optimize partial product generator circuit. The Radix 4 Kogge Stone parallel prefix adder using Heuristic Euler path method is a dopted to optimize 64 bit carry look ahead adder. With full custom design in SMIC 0. 18 trm 1P4M CMOS process, the multiplier＇ s area is O. 179 41 mm2. In a large number of test patterns, the computation time is 3. 252 ns in the worst case.
出处
《福州大学学报（自然科学版）》
CAS
CSCD
北大核心
2012年第5期602-608,共7页
Journal of Fuzhou University(Natural Science Edition)
基金
福建省自然科学基金资助项目(2012J01269)
福建省区域科技重大资助项目(2009HZ010002)
关键词
高性能乘法器
压缩器
传输门逻辑
欧拉路径法
high -performance muhiplier
compressor
transmission gate logic
Euler algorithm
