期刊文献+

SOC设计SI分析优化方法研究

Research of SI analysis and optimization for SOC design
在线阅读 下载PDF
导出
摘要 基于集成电路规模与设计工艺不断发展的现状,SI问题日益突出和严重。系统介绍了SOC设计SI的概念、分类及产生基理,根据电路工程设计经验,重点阐述了在SOC设计SI的设计、优化、分析方法,介绍了利用EDA设计工具在芯片设计过程中对SI进行阻止、优化、分析的流程及方法,并对各种设计优化方法进行了利弊的对比分析,对芯片设计提供了很好的指导,结合EDA工具及合理的设计流程方法能够有效的保证芯片设计的良率和性能。 As the continuous development of integrated circuit design and the design process, SI Issues have become increasingly prominent and serious. Introduce the concept,classes and generated reason of SI (signal integrity). In the base of circuit design experience, focus on the methods of prevent,fix and analysis during SOC design, analyze the disadvantage and advantage of every method. Can effectively guarantee the chip design and yield performance in the base of EDA tool and reasonable design method flow.
作者 李春伟
出处 《电子设计工程》 2012年第6期26-28,共3页 Electronic Design Engineering
关键词 信号完整性 双倍间距 功能噪声 延迟噪声 时序窗口 SI double space function noise delay noise timing window
  • 相关文献

参考文献6

二级参考文献21

  • 1RABAEYM.数字集成电路设计透视[M].北京:清华大学出版社,1999.471-475.
  • 2[1]Kenneth L.Shepard,Vinod Narayanan,Ron Rose.Harmony:Static Noise Analysis of Deep Submicron Digital Integrated Circuits.IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems,VOL.18,NO.8,Aug.1999,pp.1132-1150
  • 3[2]I.Catt.Crosstalk (noise) in digital systems.IEEE Transactions on Electronic Computers,vol.16,No.6,1967,pp.743□763
  • 4[3]Rafi Levy,David Blaauw,Gabi Braca,etc.ClariNet:A noise analysis tool for deep submicron design.DAC 2000,pp223-238
  • 5[4]Ravishankar Arunachalam,Karthik Rajagopal,and Lawrence T.Pileggi.TACO:Timing Analysis With Coupling.DAC 2000,pp.266-269.
  • 6[5]Ravishankar Arunachalam,Karthik Rajagopal,and Lawrence T.Pileggi.False coupling interactions in static timing analysis.DAC 2001,pp.726-731.
  • 7[6]A.Devgar.Efficient coupled noise estimation for on-chip interconnects.ICCAD,Nov.1997,pp.147-153
  • 8[7]Q.Yu,E.Kuh.Moment computation of lumped and distributed coupled RC trees with application to delay and crosstalk estimation.Proc.of the IEEE,vol.89,No.5,May 2001,pp.772-788
  • 9[8]B.Chen,H.Z.Yang,and H.Wang.Noise estimation for deep sub-micron integrated circuits.Sci.China F,Vol44,Oct.2001,pp.397-400.
  • 10[9]E.Acar,A.Odabasioglu,M.Celik,etc.S2P:a stable 2-pole RC delay and coupling noise metric.Proc.Ninth Great Lakes Symposium on VLSI,March 1999,pp.60-63

共引文献9

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部