摘要
提出了一种考虑了布线延迟的片上系统设计流程， 并运用一个新的、全芯片的、门级静态时序分析工具支持片上系统设计。实例设计表明， 该设计方法能使设计者得到更能反映实际版图的延迟值， 验证结果更完整、准确，
This paper presents the design flow for system on chip(SOC).In this process we not only synthesize our design using actual interconnect delay information,but also use a new,full chip,gate level static timing analysis tool to implement large,SOC designs.We can conclude from the experiment that our method enable designers to accurately analyze the entire chip,converge quickly on meeting timing constraints.
出处
《半导体技术》
CAS
CSCD
北大核心
1999年第6期52-55,共4页
Semiconductor Technology
关键词
系统芯片
静态时序分析
集成电路
设计
SOC design Deep submicron technology Static timing analysis
