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混合模块TC^2CLA无等待时间序列及性质

Hybrid-Modules TC^2CLA Without Waiting Time Sequence and it′s Properties
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摘要 在不增加顶层进位级联超前进位加法器(TC2CLA)模块延迟时间的条件下,为最大限度地扩展操作位数,在分析混合模块TC2CLA的延迟时间公式的基础上提出了混合模块顶层级联超前进位加法器无等待时间序列.给出了混合模块TC2CLA无等待时间序列和无等待时间完全序列的定义,推证出序列的延迟时间公式及一系列重要性质. The hybrid modules Top-level Carry Cascade Carry Lookahead Adders(TC^2CLA) without waiting time sequence was advanced on the basis of analysis delay time formula of hybrid modules TC^2CLA for purpose of the fullest expanding operand bit of TC^2CLA under conditions of not raising delay time of TC^2CLA.The definitions of hybrid modules TC^2CLA without waiting time sequence and without waiting time complete sequence were given,and the delay time formula and it′s a series of important properties were deduced.
作者 王元媛 黄娟
出处 《微电子学与计算机》 CSCD 北大核心 2011年第7期13-16,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(10926102) 中国地质大学优秀青年教师计划(CUGQNL099)
关键词 顶层进位级联超前进位加法器 混合模块 无等待时间序列 延迟时间公式 TC^2CLA hybrid module without waiting time sequence delay time formula
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参考文献8

  • 1Huong Yenmou, James B Kuo. A high--speed condi-tional carry select(CCS)adder circuit with a Successively incremented carry number block (SICNB) structure for low--voltage VLSI implementation [J].IEEE Transac- tions on Circuits and systems, 2000, 47 (10): 1074-1079.
  • 2Bui Hungtien, Wang Yuke, Jiang Yingtao. Design and analysis of low--power 10--transislor full adders using novel XOR--XNOR gates [J]. IEEE Transactions on Circuits and systems, 2002,49(1);25-30.
  • 3贾嵩,刘飞,刘凌,陈中建,吉利久.对数跳跃加法器的算法及结构设计[J].电子学报,2003,31(8):1186-1189. 被引量:7
  • 4王礼平,王观凤.顶层进位级联CLA的算法与设计规则[J].华中科技大学学报(自然科学版),2004,32(7):88-91. 被引量:6
  • 5王元媛,王礼平.TC^2CLA的混合模块延迟公式及优化序列[J].微电子学与计算机,2008,25(11):64-67. 被引量:2
  • 6Wang C, Lee PoMing, Lee Rongchin, et al. A 1. 25GHz 32bit tree- structured carry lookahead adder [C]//IEEE Intel Synop On Circuits and Systems. Syd- ney, Australia.. IEEE, 2001,4 : 80-83.
  • 7Wang Yuke, Pai C, Song Xiaoyax The design of hybrid carry--lookahead/carry--select adders [J]. IEEE Transac tions on Circuits and systems, 2002,49 (1) : 16- 24.
  • 8王元媛,王礼平.混合模块无等待时间序列超前进位加法器设计[J].微电子学与计算机,2005,22(12):12-15. 被引量:3

二级参考文献28

  • 1王礼平,王观凤.顶层进位级联CLA的算法与设计规则[J].华中科技大学学报(自然科学版),2004,32(7):88-91. 被引量:6
  • 2王礼平,王观凤.超前进位加法器的延迟时间公式与优化设计[J].武汉理工大学学报(交通科学与工程版),2004,28(4):585-588. 被引量:6
  • 3王礼平,王观凤.超前进位加法器混合模块延迟公式及优化序列[J].微电子学与计算机,2005,22(1):152-155. 被引量:4
  • 4Huang Yen- Mou, Kuo James B. A high- speed conditional carry select(CCS)adder circuit with a successively incremented carry number block(SICNB) structure for low- voltage VLSI implementation [ J ]. IEEE Transactions on Circuits and Systems, 2000,47(10):1074- 1079.
  • 5Knowles S. A family of adders[ C]//Proc. 14eh IEEE Syrup. On Computer Arithmetic. Adelaide, Australia, 1999: 277 - 284.
  • 6Wang C. A 1.25GHz 32 bit tree-structured carry lookahead adder[C]//IEEE Intl. Syrup. On Circuits and Systems. Sydney, Australia,2001,4:80 - 83.
  • 7Wang Yuke, Pai C, Song Xiaoyu. The design of hybrid carrylookahead /carryselect adders[J ]. IEEE Transactions on Circuits and systems, 2002,49(1) :16- 24.
  • 8P M Kogge, et al. A parallel algorithm for the efficient solution of agenera class of recurrence equations [J]. IEEE Trans. on Computers,1973, C-22: 786 - 793.
  • 9Brent,et al.A Regular Layout for Parallel Adders [J]. IEEE Trans.on Computers, 1982, C31 (3) :260-264.
  • 10S Knowles. A family of adders [ A ]. 1999, Proc. 14th IEEE Symp. On Computer Arithmetic [C]. Adelaide, Australia. 1999.277 - 284.

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