摘要
为提高长加法器的运算速度,扩展操作位数,提出了一种加法器结构——混合模块顶层进位级联超前进位加法器(TC2CLA).该结构将层数Mj>1的CLA模块底层进位级联改为顶层超前进位单元进位级联.在CLA单元电路优化和门电路标准延迟时间tpd的基础上,由进位关键路径推导出混合模块TC2CLA的模块延迟时间公式,阐明了公式中各项的意义.作为特例,导得了相同模块TC2CLA的模块延迟时间公式.并得出和证明了按模块层数递增级联序列是混合模块TC2CLA各序列中延迟时间最短、资源(面积)占用与功耗不变的速度优化序列.这一结论成为优化设计的一个设计规则.还给出了混合模块级联序列数的公式和应用实例.TC2CLA和CLA的延迟时间公式表明,在相同模块序列和不等待(组)生成、传输信号的条件下,最高位进位延迟时间及最高位和的最大延迟时间减小.
In order to raise arithmetic speed and to expand operand bit of the long adders,the structure of top-level carry cascade carry lookahead adders（TC2CLA） of hybrid modules was presented.The structure replaced the bottom-level carry cascade of CLA modules of modular hierarchy number Mj〉1 with the top-level look ahead carry（LAC） carry cascade among modules.The modular delay time formulae of TC2CLA of hybrid modules which based on optimizing circuit unit of CLA and the standard delayed time of logic gate tpd were derived from the carry critical path.And the meaning of all terms in the formulae was expounded.As a specific example,the modular delay time formulae of TC2CLA of same modules were easily derived.The increasing sequence in compliance with modular hierarchy number was speed optimizing sequence of minimum delay time,fixed resource（area） expense and power dissipation in all cascade sequences of hybrid modules of TC2CLA.The concluding was derived and proven.It became a design rule of optimizing design.The formula of modular cascade sequence number and an application example was given.These delay time formulae of TC2CLA and CLA show that delay time of the most significant bit carry and maximum delay time of the most significant bit sum are reduced.under condition of same modular sequence and without waiting （group） generate and propagate signals in comparison with CLA.
出处
《微电子学与计算机》
CSCD
北大核心
2008年第11期64-67,71,共5页
Microelectronics & Computer
