摘要
本文给出了一种高阶全数字锁相环的级联结构形式,它通过结构简单的全数字一阶环的级联来实现高阶环路。它避免了通常的高阶锁相环中较复杂的数字滤波器,实现简单,易于集成。本文介绍了级联全数字二阶环的原理和实现,对其性能进行了理论分析和计算机仿真,最后给出一个应用实例。
A high order all digital phase locked loop with tandem structure is presented. A 2-order all digital PLL is implemented and its performance is verified by simulation. An example is given for SDH 2048Kb/s tributary recovery. Its performances are simulated and compared with the theoretical analysis.
基金
国家自然科学基金(69896242)
