摘要
介绍了传统的超前-滞后型数字锁相环提取位同步信号的原理,提出了一种改进的简单快速的位同步FPGA实现方法,该方法首先在输入码元出现的半周期内得到码元与位同步信号的相位差,在附加门、扣除门的有效时间内,该相位差控制附加、扣除脉冲的个数,使输入码元与位同步信号快速达到同步。阐述了实现方案和模块设计,并用VHDL语言编程实现,maxplusⅡ下编译、综合、仿真、下载到FPGA芯片。仿真及实验表明:位同步建立时间只需一个码元周期,位同步快速实现。
This paper introduces the principle of traditional Lead-lag digital phase-locked loop （LL-DPLL）.A improved method of bit synchronization based on FPGA is presented. Phase difference between the signal and the output is got in half code period. Using the phase difference controls the number of adding or deleting pulses in the corresponding gate？s enable time . Fast hit synchronization is realized. And the paper describes the project and modules based on FPGA ,which programmed with VHDL ,and compiled and simulated with maxplus Ⅱ. The simulation has shown that bit synchronization setting-up time is short and needs only one code period.
出处
《微计算机信息》
北大核心
2008年第29期173-175,共3页
Control & Automation
关键词
位同步
超前-滞后型数字锁相环
FPGA
VHDL
bit synchronization
Lead-lag digital phase-locked loop
field programmable gate array （FPGA）
VHSIC hardware description language（VI-IDL）
