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具有更宽安全工作区的IGBT元胞的研究与设计 被引量:3

Design of IGBT Cell with Wider Safe Operating Area
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摘要 研究了一种新的IGBT发射极元胞,并给出其设计方法。该元胞在不影响单位面积有效沟道宽度的情况下,将源衬底的P+区与源N+区并排垂直于沟道一侧放置,以缩短空穴路径。与采用深P+注入抗闩锁的传统方法相比,经过优化设计的新结构的闩锁电流增大了约8倍;在Vce为1.5 V时,单位面积电流密度增加3倍;元胞静态阻断电压也有20%的增加,从而扩展了IGBT的安全工作区,而且工艺更简单。 A novel IGBT cell structure was investigated,and its design method was optimized.The cell structure was designed with P+ and N+ region perpendicular to the direction of channel,which shortened the distance of path for hole current to flow,and therefore enhanced its anti latch-up capability.Simulation results showed that,compared to the conventional IGBT cell structure,the optimized new structure had a latch-up current approximately 8 times higher and a current density 3 times larger,for a Vce of 1.5 V.And the breakdown voltage was also increased by 20%,which made the safe operating area of IGBT wider.In addition,the fabrication process for this novel structure was further simplified.
出处 《微电子学》 CAS CSCD 北大核心 2010年第6期904-907,共4页 Microelectronics
关键词 绝缘栅双极型晶体管 抗闩锁 安全工作区 IGBT Anti latch-up Safe operating area
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  • 1ZENG J,MAWBY P A, TOWERS M S, et al. Design of IGBTs for latch-up free operation [J]. Sol Sta Elec, 1994, 37(8): 1471-1475.
  • 2RUSSELL J P, GOODMAN A M, GOODMAN L A, et al. The COMFET-a new high conductance MOS-gated device[J]. IEEE Elec Dev Lett, 1983, 4(3) : 63-65.
  • 3BALIGA B J,ADLER M S, GRAY P V, et al. Suppressing latch up in insulated gate transistors [J]. IEEE Elec Dev Lett, 1984, 5(8) : 323-325.
  • 4NARESH T, BALIGA B J. A new IGBT structure with a wider safe operating area(SOA) [C] // IEEE Int Symp Power Semicond Dev & ICs. 1994: 177-182.
  • 5AKIO N, HIROMICHI O, MAMORU K, et al. Nonlatch-up 1200 V 75 A bipolar-mode MOSFET with large ASO [C]// Int Elec Dev Meet. 1984: 860-861.
  • 6YILIMAZ H. Cell geometry effect on IGBT latch-up [J]. Elec Dev Lett, 1985, 6(8) 419-421.
  • 7TRIVEDI M, SHENAI K. IGBT dynamics for clamped inductive switching[J]. IEEE Trans Elec Dev, 1998, 45 (12) : 2537-2545.
  • 8陈星弼.功率MOSFET和高压集成电路[M].南京:东南大学出版社,1990..
  • 9SHEN Z J, ROBB S P. Design and modeling of the 600 V IGBT with emitter ballast resistor [C]// 53rd Ann Device Research Conf. 1995: 108-109.
  • 10YUN C, KIM S, KWON Y, et al. High performance 1200 V PT IGBT with improved short-circuit immunity [C]//Proc 10th Int Symp Power Semicond Dev and ICs. 1998: 262-264.

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  • 1BALIGA B J. Modern power devices [M]. New York:Wily, 1987.
  • 2LASKA T, MUNZER M, PFIRSCH F, et al. The field stop IGBT (FS IGBT) -a new power device concept with a great improvement potential [C] ff Proceed 12th Int Symp Power Semicond Dev & IC's. Toulouse, France. 2000: 355-358.
  • 3BREGLIO G, IRACE A, Experimental detection and NAPOLI E, et al. numerical validation of different failure mechanisms in IGBTs during unclamped inductive switching [J]. IEEE Trans Elec Dev, 2013, 60(9.): 563-570.
  • 4EBERLE W, ZHANG Z L, LIU Y F, et al. A simpleswitching loss model for buck voltage regulators with current source drive [C]// IEEE Power Elec Specialists Conf. Rhodes, Greece. 2008: 3780-3786.
  • 5BARADAI N E, SANFILIPPO C, CARTA R, et al. An improved methodology for the CAD optimization of multiple floating field-limiting ring terminations [J]. IEEE Trans Elec Dev, 2011, 58(1) : 266-270.
  • 6KLUCHNIKOV A S, KRASUKOV A Y. Application of field plate to increase breakdown voltage of DMOS [C] ff 8th Int Siberian Russian Workshop&Tutorials EDM. Erlagol, Altai. 2007, 107-108.
  • 7JAUME D, CHARITAT G, REYNES J M, et al High-voltage planar devices using field plate and sem resistive layers [J]. IEEE Trans Elec Dev, 1991, 3 (7) : 1681-1684.
  • 8BURTE E P, SCHULZE G H. The correlation between the breakdown voltage of power devices passivated by semi-insulating polycrystalline silicon and the effective density of interface charges [J]. IEEE Trans Elec Dev, 1991, 38(6) : 1505-1509.
  • 9MIMURA A, OOHAYASHI M, MURAKAMI S, et al. High-voltage planar structure using SiO2-SIPOS- SiOz film [J]. IEEE Elec Dev Lett, 1985, 6(4) : 189- 191.
  • 10MATSUSHI T, AOKI T, OHTSU T, et al. Highly reliable high-voltage transistors by use of the SIPOS process [C] // Int Elec Dev Meet. Washington, D C, USA. 1975, 21: 826-830.

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