摘要
分析了RapidIO在多核DSP互连应用中的优势,提出了一种针对多核DSP应用的可扩展的片上网络互连结构.设计并实现了一种兼容RapidIO协议的网络接口体系结构,建立了网络接口的功能仿真模型,并在此基础上评估了网络接口的吞吐量和附加延时.
The advantage of RapidIO in multi-core DSP interconnection is analyzed and a network on chip interconnection architecture applied for multi-core DSP application is proposed in this paper. A network interface architecture compatible of RapidIO protocol is designed and inplememented.We build up the functional simulation model of the network interface, based on which the throughput and extra time delay of the network interface is appraised.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第5期9-13,共5页
Microelectronics & Computer
