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NOC路由节点VLSI设计 被引量：3

VLSI Design of Router for Network on Chip
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摘要 基于wormhole交换策略和目的地址确定性路由算法,采用三级流水线的结构实现了片上网络中的路由节点.该路由节点适用于Mesh和Torus拓扑,并采用虚通道技术增加吞吐量.在Xilinx的FPGA上实现后可知,该路由节点最高可工作在130 MHz的时钟频率上,传输带宽为20.8Gb/s. A muter with 3-stage pipeline architecture is designed for network on chip （NOC） in this paper. It is used wormhole forwarding strategy and detexministie muting algorithm and supports both Mesh and Toms topology. In order to increase throughput, the virtual charmds technology is also used. The NOC muter is implemented on Xilinx Virtex2p XC2vp30 with a maximum clock frequency of 130MHz and transmission bandwidth of 20.8Gb/s.
作者 王剑 王宏 杨志家
机构地区 中国科学院沈阳自动化研究所工业信息学重点实验室 中国科学院研究生院
出处 《微电子学与计算机》 CSCD 北大核心 2010年第1期9-12,共4页 Microelectronics & Computer
关键词 片上网络 路由节点 流水线结构 虚通道 network on chip muter pipeline architecture virtual channels
分类号 TN47 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献7

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二级参考文献7

  • 1孙利荣,蒋泽军,王丽芳.片上网络[J].计算机工程,2005,31(20):1-2. 被引量：5
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共引文献16

同被引文献16

  • 1Kim J, Nicopoulos C, Park D. A gracefully degrading and energy-efficient modular router architecture for on -chip networks[C]// Proceedings of the 33rd Annual International Symposium on Computer Architecture. Boston.. IEEE, 2006:4-15.
  • 2Das R, Mishra A K, Nicopoulos C, et ak Performance and power optimization through data compression in networkon-chip architectures[C]//Proceedings of the 14th liner- national Symposium on High Performance Computer Architecture Salt Imke City: IEEE, 2008:215-225.
  • 3Alameldeen A R, Wood D A. Interactions between compression and prefetching in chip multiprocessors[C]// Proceedings of the 13th International Symposium on High-Performance Computer Architecture. Phoenix: IEEE, 2007:228-239.
  • 4Jingcao Hu,Umit Y Ogras, Radu Marculescu. System- level buffer allocation for application-specific networks- on-chip router design[-J]. IEEE Transactions on Com- puter-Aided Design of Integrated Circuits and Sys- tems, 2006,25(12) :2919-2933.
  • 5Willian J Dally, Towles 13. Route packets, not wires: on- chip interconnection networks [C]//Proceedings of DAC 2001. I.as Vegas, USA:ACM, 2001: 684-689.
  • 6Benini I., De Micheli G. Networks on chips., a new SoC paradigrr[J] IEEE Computer, 2002, 35(1) .-70-78.
  • 7Ehliar A, Dake IAu. An FPGA based open source net- work-on-chip architecture[C]//2007 International Con - ference on Field Programmable Logic and Applica- tions. Amsterdam: IEEE, 2007 : 800-803.
  • 8Chen X, andPeh I;S. Leakage power modeling and optimization in interconneetion networks[C]//Proc Int Syrup Low Power Electronics and Design (ISLPED). New York, NY:ACM,2003= 90-95.
  • 9Hu J, Marculescu tL Application-specific buffer space allocation for networks-on-chip router design[C]// Proe IEEE/ACM Int Conf Computer-aided design (IC- CAD), USA: IEEE,2004: 354-361.
  • 10Fazzino F, Palesi M, Patti D. Noxim:network-on-chip simulator [ EB/OL]. [ 2012-11-02 ]. http://noxim. soureeforge, net, 2008.

引证文献3

二级引证文献14

微电子学与计算机
2010年 第1期

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