摘要
RS码是一种有效的差错控制编码,它能够纠正数字信号在传输和存储过程中产生的突发、随机等错误,保证数据传输和存储的有效性。利用FPGA能快速经济地把电路描述转换为硬件实现的特点,本文采用Top-Down的方法对RS码进行了FPGA的设计实现。所有结构模块均实现RTL级建模,并对其中乘法器模块和BM迭代单元给出了详细的描述。最后利用EDA工具对整个模块进行了验证综合,结果表明,符合设计需求,该方案能很好地实现RS码,并且占用硬件资源少、速度快,工作频率能达到100MHz。
RS code is an effective error control coding, it can correct the digital signal during transmission and storage process of the sudden, random and other errors, data transmission and storage to ensure effectiveness. FPGA can quickly use the circuit description of the economy into a hardware implementation of the characteristics of Top-Down in this paper,the method of RS code of the FPGA design. All structural modules to achieve RTL-level modeling, and which modules and BM iterative multiplier unit is given a detailed description. Finally, the use of EDA tools for the entire module to verify the integrated, results showed that with the design requirements, the program can achieve very good RS code, and hardware resources occupied by small, fast operating frequency can reach 100MHz.
出处
《电子测量技术》
2009年第6期143-147,共5页
Electronic Measurement Technology
