摘要
在介绍了GPS同步时钟基本原理和FPGA特点的基础上,提出了一种基于FPGA的GPS同步时钟装置的设计方案,实现了高精度同步时间信号和同步脉冲的输出,以及GPS失步后秒脉冲的平滑切换,给出了详细设计过程和时序仿真结果。
After introducing the principle of the GPS synchronous clock and the features of FPGA, this paper proposed a design scheme of a GPS synchronous clock equipment. The outputs of the synchronized time signal and synchronization pulse with high precision and the smooth switch of the One-Pulse-Per-Second after the synchronization loss of GPS were realized. The detailed design process and the simulation results were presented.
出处
《微计算机信息》
北大核心
2007年第03S期261-263,共3页
Control & Automation
