摘要
现代数字通信中为了扩大信息的传输容量并提高信道的利用率,往往采用数字复接技术;文章提出了一种基于FPGA实现同步数字复接系统的设计方案,该方案在帧同步检测的关键部分采取前方保护和后方保护的措施,很大程度上提高了系统的抗干扰能力,并采用Verilog HDL硬件描述语言完成系统各组成模块的描述,最后在Quartus II集成环境下进行了系统的综合、布局布线及时序仿真;仿真结果验证了输入输出的逻辑关系,实现了数字复接系统的模块化设计,功能稳定可靠。
In modern digital communication, the digital multiple connection technique is applied to expand the capacity of the information transmission and raise the efficiency of the channel. The paper proposes a method to design synchronous digital multiplex system based on FPGA. This method takes the forward and backward protective measures in the key part of frame synchronous detection, it greatly improved the whole system on the reliability. All of the functional modules described in Verilog HDL. Synthesis, wire placing and routing and timing simulation of the system proceed under the Quartus II IDE at last. Simulation results validates the logical relations of Input/Output, realizes the modularization design of SDM. The function of whole design is stable and reliable.
出处
《计算机测量与控制》
CSCD
2008年第8期1174-1176,共3页
Computer Measurement &Control
关键词
FPGA
数字复接
状态机
帧同步检测
FPGA
digital multiplex
state machine
frame synchronous detection
