摘要
针对800 Mb/s高速率数传系统,设计并实现了一种8PSK信号的数字定时同步算法。首先推导出高速数据的Martin Oerder包络平方定时相位误差估计算法的并行实现结构,然后采用FPGA芯片设计实现了定时偏差估计。计算机仿真和硬件实现研究的结果验证了该算法结构在高速数据传输系统下具有良好的估计性能。
To investigate the reception of 800 Mb/s high speed satellite signals,a data timing recovery algorithm is implemented for 8PSK signals. Fistly this article deduces the parallel structure of the Martin Oerder square timing recovery algorithm, then implements the function of timing estimate by the FPGA chip. Simulation and implementation results show the algorithm has good performance for the timing estimate under the high speed data rate transmission systerm.
出处
《现代电子技术》
2007年第23期1-3,共3页
Modern Electronics Technique
关键词
定时恢复
估计
并行结构
FPGA
timing recovery, estimate
parallel structure, FPGA
