摘要
时钟同步是网络通信系统中保证数据正确和有效传输的前提,广泛应用于传统电话网络、IP网络、光网络和无线传输网络等。针对目前网络时钟同步控制的复杂性,在分析网络结构、时钟控制和弹性缓冲区原理的基础上,提出一种基于FPGA、CPU和DDS技术的网络自同步时钟控制方法。通过软硬件相结合的处理方式,以最小开销实现网络时钟快速同步。然后对其原理进行了分析,给出实现的硬件框图、FPGA信号流程和CPU设计流程,并在设备和网络中进行了验证,验证结果表明该方法是正确、可行和有效的。
Clock synchronization is the precondition of correct and effective data transmission in network communication system,and is widely used in traditional telephone network,IP network,optical network and wireless transmission network.In allusion to the complexity of clock synchronization control used in current networks,a clock control method applied to automatic network synchronization is put forward on the basis of analyzing the principles of network framework,clock control and elastic buffer.The method is based on FPGA,CPU and DDS technologies.Network clock synchronization is implemented in most economy consumption by the cooperation of software and hardware.The principle is analyzed.The implemented hardware diagram,FPGA signal flowsheet and CPU design flowsheet are given in this paper.The method was tested in some equipments and networks.The test results prove that the method is correct,feasible and effective.
出处
《现代电子技术》
2013年第18期80-83,共4页
Modern Electronics Technique
