摘要
基于级联半导体光放大器(SOA)实现全光逻辑与门的方案中,第一级输出信号质量直接影响逻辑与运算结果.采用载流子恢复较慢的体材料半导体光放大器用于第一级转换,在10 Gbit/s以上得不到理想的转换结果,限制了该方案实现逻辑与门的速率.利用光纤延时干涉仪(DI)和第一级半导体光放大器级联可以改善第一级输出信号质量,从而有效提高第二级全光逻辑与门的实现速率.阐述了改进方案中延时干涉仪的作用,并进行了数值模拟.根据实验结果,采用载流子恢复较慢的半导体光放大器级联延时干涉仪能够实现高速归零(RZ)信号和非归零(NRZ)信号的反码,从而得到较高速率的全光逻辑与门.实验实现了20 Gbit/s的伪随机归零和非归零信号的全光逻辑与门,对40 Gbit/s的结果进行了分析和讨论.
In the all-optical logical AND gate based on cascaded two stage semiconductor optical amplifiers （SOAs）, the output signal from the first stage has notable impact on the final result. When the bulk material SOA with a slow carrier-recovery process is used in the first-stage conversion, the conversion speed beyond 10 Gibt/s can not be reached perfectly, so the speed of all optical logical AND operation is limited. The first stage output signal will be improved when a delayed interferometer （DI） is cascaded after the first stage SOA, and the second-stage all-optical logical AND gate operation will also benefit from the DI cascade. The function of the DI in the revised scheme is illustrated and simulated. In experiments, inverted-signals of high-speed return-to-zero （RZ） signals and non return to-zero （NRZ） signals are realized by the modified scheme, so a high-speed all-optical logical AND gate is achieved. All-optical logical AND gate operation at 20 Gbit/s for pseudo-random RZ signals and NRZ signals is demonstrated experimentally, and the results at 40 Gbit/s are also analyzed.
出处
《中国激光》
EI
CAS
CSCD
北大核心
2007年第11期1517-1521,共5页
Chinese Journal of Lasers
基金
湖北省杰出青年基金(2006ABB017)
教育部新世纪优秀人才(NCET-04-0715)资助项目
关键词
光电子学
全光逻辑与门
半导体光放大器
延时干涉仪
optoelectronics
all-optical logic AND gate
semiconductor optical amplifier
delayed interferometer
