摘要
针对当前网络与通信领域对于信息安全的广泛需求,以普遍使用的DES加密算法为研究对象,面对百兆以太网等中低端应用,利用现有的SPARTAN IIE FPGA加以实现。在系统设计中,对算法系统性能、资源占用和通用性进行了综合考虑,根据实际硬件进行优化,提出了资源占用率低、加密速度快的解决方案,并由硬件验证其正确性。
With the urgent need for the information security in the field of networks and communication, it is very important to put an easy-to-realize encrypt algorithm such like DES into practical use. We realized the DES on SPARTANIIE FPGA considering the systematical algorithm performance, the generality of the algorithm and the resource usage as a whole. Moreover, this paper proposed an efficient method to lower the＇resource usage considering the practical hardware environment. And the experimental results showed its correctness and efficiency.
出处
《电子器件》
EI
CAS
2006年第3期895-897,901,共4页
Chinese Journal of Electron Devices
