摘要
以EP1S20F672C7为核心，利用PLX9054作为密码卡与主机交换数据的接口芯片，采用多个硬件线程并行处理实现3DES算法，设计了3DES密码卡。介绍了硬件的构成、原理图的设计、底层软件的编程以及密码算法IP核的开发。所设计的IP核具有很高的灵活性，可同时处理1～53个任务。
Cipher card based on multi-thread 3DES algorithm is designed. The kernel of hardware is EP1S20F672C7. PLX9054 is used as the bridge chip of data exchange between cipher card and host PC. The structure of hardware, the design of principle graph, the program of software and the IP kernel of cipher algorithm are introduced. Designed IP kernel has higher flexibility, and can process 1 -53 tasks at the same time.
出处
《计算机工程》
CAS
CSCD
北大核心
2006年第11期253-255,共3页
Computer Engineering
基金
2004年广州市属高校科技计划基金资助项目(2003)
