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集成电路多层铜布线阻挡层CMP技术与材料 被引量:2

Technology and Slurry of Barrier CMP in ULSI with Cu Interconnection
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摘要 以化学机械全局平面化(CMP)动力学过程和机理为基础,在抛光浆料中采用粒径为1 5~20nm的硅溶胶作为CMP磨料,保证了高的抛光速率(200nm/min),同时可有效降低表面粗糙度,减少损伤层的厚度。 The smaller size ranging from 15-20nm silica sols is chosen as abrasive, which is based on the investigation of the polishing kinetics process and mechanism of CMP. The polishing slurry with smaller abrasive and polishing technology effectively can reduce the roughness and thickness of the damaged layer and also afford high polishing rate (200nm/min).
出处 《半导体技术》 CAS CSCD 北大核心 2006年第5期334-336,345,共4页 Semiconductor Technology
基金 国家自然科学基金资助项目(60176033) 河北省自然科学基金资助项目(502029)
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参考文献5

  • 1RYU C,LEE H,KWON K W,et al.Barriers for copper interconnections[J].Solid State Technology,1999,42(4):53-56.
  • 2ZHANG G H,QIAN H,GAO W F,et al.A novel barrier to copper metallization by implanting nitrogen into SiO2[J].Chinese J of Semiconductors,2001,22(3):271-274.
  • 3DINGP J,CHEN L,FU J M,et al.Cu barrier/seed technology development for sub-0.10 micron copper chips[J].Solid-state and Integrated Circuit Technology processing,2001,1:405-409.
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