A multisampling technique was introduced to the phase error detector of Conventional Digital Tanlocked Loop(C DTL). In this new technique a number of samples ( M ) were taken at nonuniform intervals within one peri...A multisampling technique was introduced to the phase error detector of Conventional Digital Tanlocked Loop(C DTL). In this new technique a number of samples ( M ) were taken at nonuniform intervals within one period of the input signal. The novel system is called Multisampling Digital Tanlocked loop(MS DTL). The simulated model on the computer shows that for M =4, the system has a faster locking speed and wider locking in range compared with C DTL.展开更多
A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor...A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.展开更多
文摘A multisampling technique was introduced to the phase error detector of Conventional Digital Tanlocked Loop(C DTL). In this new technique a number of samples ( M ) were taken at nonuniform intervals within one period of the input signal. The novel system is called Multisampling Digital Tanlocked loop(MS DTL). The simulated model on the computer shows that for M =4, the system has a faster locking speed and wider locking in range compared with C DTL.
基金Supported by the National High Technology Re-search and Development Programof China (2004AA122310)
文摘A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.
