High-density interconnect(HDI)soft electronics that can integrate multiple individual functions into one miniaturized monolithic system is promising for applications related to smart healthcare,soft robotics,and human...High-density interconnect(HDI)soft electronics that can integrate multiple individual functions into one miniaturized monolithic system is promising for applications related to smart healthcare,soft robotics,and human-machine interactions.However,despite the recent advances,the development of three-dimensional(3D)soft electronics with both high resolution and high integration is still challenging because of the lack of efficient manufacturing methods to guarantee interlayer alignment of the high-density vias and reliable interlayer electrical conductivity.Here,an advanced 3D laser printing pathway,based on femtosecond laser direct writing(FLDW),is demonstrated for preparing liquid metal(LM)-based any layer HDI soft electronics.FLDW technology,with the characteristics of high spatial resolution and high precision,allows the maskless fabrication of high-resolution embedded LM microchannels and high-density vertical interconnect accesses for 3D integrated circuits.High-aspect-ratio blind/through LM microstructures are formed inside the elastomer due to the supermetalphobicity induced during laser ablation.The LM-based HDI circuit featuring high resolution(~1.5μm)and high integration(10-layer electrical interconnection)is achieved for customized soft electronics,including various customized multilayer passive electric components,soft multilayer circuit,and cross-scale multimode sensors.The 3D laser printing method provides a versatile approach for developing chip-level soft electronics.展开更多
The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performa...The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.展开更多
基金supported by the National Science Foundation of China under the Grant Nos.12127806 and 62175195the International Joint Research Laboratory for Micro/Nano Manufacturing and Measurement Technologies。
文摘High-density interconnect(HDI)soft electronics that can integrate multiple individual functions into one miniaturized monolithic system is promising for applications related to smart healthcare,soft robotics,and human-machine interactions.However,despite the recent advances,the development of three-dimensional(3D)soft electronics with both high resolution and high integration is still challenging because of the lack of efficient manufacturing methods to guarantee interlayer alignment of the high-density vias and reliable interlayer electrical conductivity.Here,an advanced 3D laser printing pathway,based on femtosecond laser direct writing(FLDW),is demonstrated for preparing liquid metal(LM)-based any layer HDI soft electronics.FLDW technology,with the characteristics of high spatial resolution and high precision,allows the maskless fabrication of high-resolution embedded LM microchannels and high-density vertical interconnect accesses for 3D integrated circuits.High-aspect-ratio blind/through LM microstructures are formed inside the elastomer due to the supermetalphobicity induced during laser ablation.The LM-based HDI circuit featuring high resolution(~1.5μm)and high integration(10-layer electrical interconnection)is achieved for customized soft electronics,including various customized multilayer passive electric components,soft multilayer circuit,and cross-scale multimode sensors.The 3D laser printing method provides a versatile approach for developing chip-level soft electronics.
基金supported by the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDA06010401the National Natural Science Foundation of China under Grant Nos.61202056,61331008,61221062the HuaweiResearch Program of China under Grant No.YBCB2011030
文摘The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.
