We investigate the impact of high-energy O ions on the occurrence of single-event burnout(SEB) in silicon carbide(Si C) metal–oxide–semiconductor field-effect transistors(MOSFETs) under various bias conditions. Thro...We investigate the impact of high-energy O ions on the occurrence of single-event burnout(SEB) in silicon carbide(Si C) metal–oxide–semiconductor field-effect transistors(MOSFETs) under various bias conditions. Through a combination of SRIM, GEANT4, and TCAD simulations, we explore the role of secondary ions generated by nuclear reactions between high-energy O ions and Si C materials. These secondary ions, with significantly higher linear energy transfer(LET) values, contribute to electron–hole pair generation, leading to SEB. Our results show that the energy deposition and penetration depth of these secondary ions, especially those with high LET, are sufficient to induce catastrophic SEB in Si C MOSFETs. The study also highlights the critical influence of reverse bias voltage on SEB occurrence and provides insights into the failure mechanisms induced by nuclear reactions with high-energy O ions. This work offers valuable understanding for improving the radiation resistance of Si C-based power devices used in space and high-radiation environments,contributing to the design of more reliable electronics for future space missions.展开更多
This paper presents a comprehensive analysis of the short-circuit failure mechanisms in commercial 1.2 kV planar sili-con carbide(SiC)metal–oxide–semiconductor field-effect transistors(MOSFETs)under 400 and 800 V bu...This paper presents a comprehensive analysis of the short-circuit failure mechanisms in commercial 1.2 kV planar sili-con carbide(SiC)metal–oxide–semiconductor field-effect transistors(MOSFETs)under 400 and 800 V bus voltage conditions.The study compares two products with varying short-circuit tolerances,scrutinizing their external characteristics and intrinsic fac-tors that influence their short-circuit endurance.Experimental and numerical analyses reveal that at 400 V,the differential ther-mal expansion between the source metal and the dielectric leads to cracking,which in turn facilitates the infiltration of liquid metal and results in a gate–source short circuit.At 800 V,the failure mechanism is markedly different,attributed to the ther-mal carrier effect leading to the degradation of the gate oxide,which impedes the device's capacity to switch off,thereby trig-gering thermal runaway.The paper proposes strategies to augment the short-circuit robustness of SiC MOSFETs at both volt-age levels,with the objective of fortifying the device's resistance to such failures.展开更多
Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require car...Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require careful studies to foster their development.In this work,we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs(TMOS’s)provided by TCAD simulations,enhancing the dependability of the adopted process optimization approaches.Specifically,two different TMOS devices are compared in terms of transfer-curve hysteresis(H)and subthreshold slope(SS),showing a≈75%H reduction along with a≈30%SS decrease.Simulations allow attributing the achieved improvements to a decrease in the border and interface traps,respectively.A sensitivity analysis is also carried out,allowing to quantify the additional trap density reduction required to minimize both figures of merit.展开更多
A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving...A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving the 2D Poisson＇s equation. The minimum of the potential at the oxide-Si layer interface is used to monitor the threshold voltage of the SOI MOSFETs. This model is verified by its excellent agreement with MEDICI simulation using SOI MOSFETs with different gate lengths,gate oxide thicknesses,silicon film thicknesses,and channel doping concentrations.展开更多
随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了...随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。展开更多
A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential dis...A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson＇s equation with suitable boundary conditions. The minimum of the surface potential is used to deduce the threshold voltage model. The model reveals the variations of potential distribution and threshold voltage with temperature, taking into account short-channel effects. Furthermore, the model is verified by the SILVACO ATLAS simulation. The calculations and the simulation agree well.展开更多
Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristic...Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristics and the breakdown voltage are studied in detail. Through simulations,it is found that the AC PD SOI device can suppress the floating effects and improve the breakdown characteristics over conventional partially depleted silicon-on-insulator devices. Also compared to the reported AC FD SOI device,the performance variation with device parameters is more predictable and operable in industrial applications. The AC FD SO1 device has thinner silicon film, which causes parasitical effects such as coupling effects between the front gate and the back gate and hot electron degradation effects.展开更多
Recent developments in the use of diamond materials as metal-oxide-semiconductor field-effect transistors (MOSFETs) are in- troduced in this article, including an analysis of the advantages of the device owing to the ...Recent developments in the use of diamond materials as metal-oxide-semiconductor field-effect transistors (MOSFETs) are in- troduced in this article, including an analysis of the advantages of the device owing to the unique physical properties of diamond materials, such as their high-temperature and negative electron affinity characteristics. Recent research progress by domestic and international research groups on performance improvement of hydrogen-terminated and oxygen-terminated diamond-based MOSFETs is also summarized. Currently, preparation of large-scale diamond epitaxial layers is still relatively difficult, and improvements and innovations in the device structure are still ongoing. However, the key to improving the performance of diamond-based MOSFET devices lies in improving the mobility of channel carriers. This mainly includes improvements in doping technologies and reductions in interface state density or carrier traps. These will be vital research goals for the future of diamond-based MOSFETs.展开更多
On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- s...On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.展开更多
A compact model for the integrated inversion charge density Qi in double-gate （DG-） MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on...A compact model for the integrated inversion charge density Qi in double-gate （DG-） MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on the previous work of Ge, we establish an expression for the surface potential with respect to Qi, and form an implicit equation, from which Qi can be solved. Results predicted by our model are compared to published data as well as results from Schred,a popular 1D numerical solver that solves the Poisson＇s and Schr6dinger equa- tions self-consistently. Good agreement is obtained for a wide range of silicon layer thickness,confirming the supe- riority of this model over previous work in this field.展开更多
Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface chann...Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.展开更多
A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, wher...A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 12035019 and 62234013)the National Key Research and Development Program of China(Grant Nos. 2023YFA1609000 and 2022YFB3604001)。
文摘We investigate the impact of high-energy O ions on the occurrence of single-event burnout(SEB) in silicon carbide(Si C) metal–oxide–semiconductor field-effect transistors(MOSFETs) under various bias conditions. Through a combination of SRIM, GEANT4, and TCAD simulations, we explore the role of secondary ions generated by nuclear reactions between high-energy O ions and Si C materials. These secondary ions, with significantly higher linear energy transfer(LET) values, contribute to electron–hole pair generation, leading to SEB. Our results show that the energy deposition and penetration depth of these secondary ions, especially those with high LET, are sufficient to induce catastrophic SEB in Si C MOSFETs. The study also highlights the critical influence of reverse bias voltage on SEB occurrence and provides insights into the failure mechanisms induced by nuclear reactions with high-energy O ions. This work offers valuable understanding for improving the radiation resistance of Si C-based power devices used in space and high-radiation environments,contributing to the design of more reliable electronics for future space missions.
基金supported by the Science and Technology Innovation Key R&D Program of Chongqing (Grant No.2023TIADSTX0037)the National Natural Science Foundation of China (Grant No.62404026)+1 种基金the General Program of National Natural Science Foundation of Chongqing (Grant Nos.CSTB2023NSCQ-MSX0475,CSTB2024NSCQ-MSX0331)the Science and Technology Research Program of Chongqing Municipal Education Commission (Grant No.KJQN202400609).
文摘This paper presents a comprehensive analysis of the short-circuit failure mechanisms in commercial 1.2 kV planar sili-con carbide(SiC)metal–oxide–semiconductor field-effect transistors(MOSFETs)under 400 and 800 V bus voltage conditions.The study compares two products with varying short-circuit tolerances,scrutinizing their external characteristics and intrinsic fac-tors that influence their short-circuit endurance.Experimental and numerical analyses reveal that at 400 V,the differential ther-mal expansion between the source metal and the dielectric leads to cracking,which in turn facilitates the infiltration of liquid metal and results in a gate–source short circuit.At 800 V,the failure mechanism is markedly different,attributed to the ther-mal carrier effect leading to the degradation of the gate oxide,which impedes the device's capacity to switch off,thereby trig-gering thermal runaway.The paper proposes strategies to augment the short-circuit robustness of SiC MOSFETs at both volt-age levels,with the objective of fortifying the device's resistance to such failures.
基金funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU),under grant agreement No.101007229support from the European Union’s Horizon 2020 Research and Innovation Programme,Germany,France,Belgium,Austria,Sweden,Spain,and Italy
文摘Vertical GaN power MOSFET is a novel technology that offers great potential for power switching applications.Being still in an early development phase,vertical GaN devices are yet to be fully optimized and require careful studies to foster their development.In this work,we report on the physical insights into device performance improvements obtained during the development of vertical GaN-on-Si trench MOSFETs(TMOS’s)provided by TCAD simulations,enhancing the dependability of the adopted process optimization approaches.Specifically,two different TMOS devices are compared in terms of transfer-curve hysteresis(H)and subthreshold slope(SS),showing a≈75%H reduction along with a≈30%SS decrease.Simulations allow attributing the achieved improvements to a decrease in the border and interface traps,respectively.A sensitivity analysis is also carried out,allowing to quantify the additional trap density reduction required to minimize both figures of merit.
基金Supported by the National Natural Science Foundation of China(No.60576066,No.60644007)the Natural Science Foundation of Anhui Province(No.2006kj012a).
文摘A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving the 2D Poisson＇s equation. The minimum of the potential at the oxide-Si layer interface is used to monitor the threshold voltage of the SOI MOSFETs. This model is verified by its excellent agreement with MEDICI simulation using SOI MOSFETs with different gate lengths,gate oxide thicknesses,silicon film thicknesses,and channel doping concentrations.
文摘随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。
基金Project supported by Key Project of National Natural Science Foundation of China（50531060） National Science Found for Distinguished Young Scholars of China（10525211）+2 种基金 National Natural Science Foundation of China（10572124 10472099） Key Project of Scientific and Technological Department of Hunan Province （05FJ2005）, and the Open Project Program of Low Dimensional Materials ＆ Application Technology （Xiangtan University）, Ministry of Education, China （KF0602）.
文摘A temperature-dependent model for threshold voltage and potential distribution of fully depleted silicon-on- insulator metal-oxide-semiconductor field-effect transistors is developed. The two-dimensional potential distribution function in the silicon thin film based on an approximate parabolic function has been applied to solve the two-dimensional Poisson＇s equation with suitable boundary conditions. The minimum of the surface potential is used to deduce the threshold voltage model. The model reveals the variations of potential distribution and threshold voltage with temperature, taking into account short-channel effects. Furthermore, the model is verified by the SILVACO ATLAS simulation. The calculations and the simulation agree well.
文摘Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristics and the breakdown voltage are studied in detail. Through simulations,it is found that the AC PD SOI device can suppress the floating effects and improve the breakdown characteristics over conventional partially depleted silicon-on-insulator devices. Also compared to the reported AC FD SOI device,the performance variation with device parameters is more predictable and operable in industrial applications. The AC FD SO1 device has thinner silicon film, which causes parasitical effects such as coupling effects between the front gate and the back gate and hot electron degradation effects.
基金financially supported by the National Key Research and Development Program of China (No.2018YFB0406501)the Beijing Municipal Science and Technology Commission (No. Z181100004418009)the National Natural Science Foundation of China (No.51702313)
文摘Recent developments in the use of diamond materials as metal-oxide-semiconductor field-effect transistors (MOSFETs) are in- troduced in this article, including an analysis of the advantages of the device owing to the unique physical properties of diamond materials, such as their high-temperature and negative electron affinity characteristics. Recent research progress by domestic and international research groups on performance improvement of hydrogen-terminated and oxygen-terminated diamond-based MOSFETs is also summarized. Currently, preparation of large-scale diamond epitaxial layers is still relatively difficult, and improvements and innovations in the device structure are still ongoing. However, the key to improving the performance of diamond-based MOSFET devices lies in improving the mobility of channel carriers. This mainly includes improvements in doping technologies and reductions in interface state density or carrier traps. These will be vital research goals for the future of diamond-based MOSFETs.
基金Supported by the National Natural Science Foundation of China under Grant Nos 61404151 and 61574153
文摘On the basis of a detailed discussion of the development of total ionizing dose （TID） effect model, a new commercial-model-independent TID modeling approach for partially depleted silicon-on-insulator metal-oxide- semiconductor field effect transistors is developed. An exponential approximation is proposed to simplify the trap charge calculation. Irradiation experiments with 60Co gamma rays for IO and core devices are performed to validate the simulation results. An excellent agreement of measurement with the simulation results is observed.
文摘A compact model for the integrated inversion charge density Qi in double-gate （DG-） MOSFETs is developed. For nanoscale applications,quantum confinement of the inversion carriers must be taken into account. Based on the previous work of Ge, we establish an expression for the surface potential with respect to Qi, and form an implicit equation, from which Qi can be solved. Results predicted by our model are compared to published data as well as results from Schred,a popular 1D numerical solver that solves the Poisson＇s and Schr6dinger equa- tions self-consistently. Good agreement is obtained for a wide range of silicon layer thickness,confirming the supe- riority of this model over previous work in this field.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.
文摘A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.
