本文提出了一种适用于5G通信的14 bit 100 MS/s的Pipelined-SAR ADC设计,包括采样保持模块、第一级6 bit SAR ADC、残差放大器、第二级9 bit SAR ADC和数字冗余矫正模块等结构。其中,采用了一种新型高速高精度全动态比较器来提高SAR AD...本文提出了一种适用于5G通信的14 bit 100 MS/s的Pipelined-SAR ADC设计,包括采样保持模块、第一级6 bit SAR ADC、残差放大器、第二级9 bit SAR ADC和数字冗余矫正模块等结构。其中,采用了一种新型高速高精度全动态比较器来提高SAR ADC的转换速率与转换精度;采用基于Gain-boosting技术的全差分双输入对管运算放大器提升残差放大器的输入摆幅、增益与GBW。使用TSMC 65 nm CMOS工艺进行仿真与验证。结果表明,在1.2 V电源电压和100 MS/s的转换速率下,本设计达到了78.95 dB的SNDR和12.82 bit的ENOB,在精度相同的情况下与传统SAR ADC相比大幅提升了转换速率,该设计可以满足高速高精度的数据采集应用场景。展开更多
A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor...A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.展开更多
A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operation...A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.展开更多
This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications ...This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.展开更多
文摘本文提出了一种适用于5G通信的14 bit 100 MS/s的Pipelined-SAR ADC设计,包括采样保持模块、第一级6 bit SAR ADC、残差放大器、第二级9 bit SAR ADC和数字冗余矫正模块等结构。其中,采用了一种新型高速高精度全动态比较器来提高SAR ADC的转换速率与转换精度;采用基于Gain-boosting技术的全差分双输入对管运算放大器提升残差放大器的输入摆幅、增益与GBW。使用TSMC 65 nm CMOS工艺进行仿真与验证。结果表明,在1.2 V电源电压和100 MS/s的转换速率下,本设计达到了78.95 dB的SNDR和12.82 bit的ENOB,在精度相同的情况下与传统SAR ADC相比大幅提升了转换速率,该设计可以满足高速高精度的数据采集应用场景。
文摘A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
文摘A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.
文摘This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.
