摘要
本文提出了一种适用于5G通信的14 bit 100 MS/s的Pipelined-SAR ADC设计,包括采样保持模块、第一级6 bit SAR ADC、残差放大器、第二级9 bit SAR ADC和数字冗余矫正模块等结构。其中,采用了一种新型高速高精度全动态比较器来提高SAR ADC的转换速率与转换精度;采用基于Gain-boosting技术的全差分双输入对管运算放大器提升残差放大器的输入摆幅、增益与GBW。使用TSMC 65 nm CMOS工艺进行仿真与验证。结果表明,在1.2 V电源电压和100 MS/s的转换速率下,本设计达到了78.95 dB的SNDR和12.82 bit的ENOB,在精度相同的情况下与传统SAR ADC相比大幅提升了转换速率,该设计可以满足高速高精度的数据采集应用场景。
This article proposes a 14 bit 100 MS/s Pipelined SAR ADC design suitable for 5G commu⁃nication,including a sampling and holding module,a first stage 6 bit SAR ADC,a residual amplifier,a second stage 9 bit SAR ADC,and a digital redundancy correction module.Among them,a new type of high-speed and high-precision full dynamic comparator was adopted to improve the conversion rate and accuracy of SAR ADC;Adopting a fully differential dual input transistor operational amplifier based on Gain boosting technology to enhance the input swing,gain,and GBW of the residual amplifier.Simulate and verify using TSMC 65 nm CMOS technology.The results show that at a power supply voltage of 1.2 V and a conversion rate of 100 MS/s,this design achieves a SNDR of 78.95 dB and an ENOB of 12.82 bit,sig⁃nificantly improving the conversion rate compared to traditional SAR ADCs with the same accuracy.This design can meet high-speed and high-precision data acquisition application scenarios.
作者
卢炫霖
申人升
LU Xuanlin;SHEN Rensheng(Integrated Circuit School,Dalian University of Technology,Dalian 116000,China)
出处
《微处理机》
2025年第4期31-34,共4页
Microprocessors
基金
国家重点研发计划项目“高能效感算一体芯片与系统”(2023YFB4503003)
辽宁省科技计划联合计划项目(2024JH2/102600042)
关键词
模数转换器
动态比较器
流水线
增益提升技术
残差放大器
analog-to-digital converter
dynamic comparator
pipelined
gain-boosting technology
residue amplifier
