A low power digital operational transconductance amplifier （OTA） was developed for low voltage switched capacitor applications. The OTA has a high slew rate （SR） and a large open loop gain with a dif- ferential ps...A low power digital operational transconductance amplifier （OTA） was developed for low voltage switched capacitor applications. The OTA has a high slew rate （SR） and a large open loop gain with a dif- ferential pseudo-two-stage Class-AB structure. A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal （MIM） capacitor to reduce the fabrication cost. Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal, this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing. The slew rate is ±16.29V/μs and the total power dissipation is only 82 μW.展开更多
A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating b...A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.展开更多
A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides ...A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.展开更多
基金Supported by the National Natural Science Foundation of China(No.60236020)the Specialized Research Fund for the Doctoral Program of Higher Education (No.20050003083)
文摘A low power digital operational transconductance amplifier （OTA） was developed for low voltage switched capacitor applications. The OTA has a high slew rate （SR） and a large open loop gain with a dif- ferential pseudo-two-stage Class-AB structure. A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal （MIM） capacitor to reduce the fabrication cost. Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output terminal, this digital differential pseudo-two-stage Class-AB OTA realized in 0.13-μm technology achieves a 63.5-dB DC gain and a 0.83-V output swing. The slew rate is ±16.29V/μs and the total power dissipation is only 82 μW.
基金supported by the National High Technology Research and Development Program of China(No.2009AA042321)
文摘A 14 bit 51.2 kS/s extended counting analog to digital converter （EC-ADC） is presented. Two techniques are utilized to reduce its power consumption. First, a double-sampling configuration based on a fully-floating bilin- ear integrator is proposed to reduce the clock frequency. Second, a class-AB operational transconductance amplifier （OTA） is designed to improve the power efficiency. In addition, the chopping technique is used to eliminate the OTA flicker noise effect. The proposed ADC is fabricated in 0.18 μm CMOS technology with a core area of 0.04 mm2. At a 51.2 kS/s conversion rate, it achieves a 94 dB SFDR and an 11.6 bit ENOB, while consuming only 77 μW from a 1.8 V power supply. The figure of merit is only 0.48 p J/step.
基金Project supported by the National Natural Science Foundation of China(Nos.61106024,61201176)
文摘A novel class-AB implementation of a current-mode programmable gain amplifier （CPGA） including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.
