摘要
设计了一种低压低功耗CMOS折叠-共源共栅运算放大器。该运放的输入级采用折叠-共源共栅结构,可以优化输入共模范围,提高增益;由于采用AB类推挽输出级,实现了全摆幅输出,并且大大降低了功耗。采用TSMC 0.18μmCMOS工艺,基于BSIM3V3 Spice模型,用HSpice对整个电路进行仿真,结果表明:与传统结构相比,此结构在保证增益、带宽等放大器重要指标的基础上,功耗有了显著的降低,非常适合于低压低功耗应用。目前,该放大器已应用于14位∑-Δ模/数转换电路的设计中。
A high - performance low - voltage and low - power CMOS folded cascode operational amplifier is designed in this paper. Folded cascode construction for the input stage is adopted. In this construction, ICMR can be optimized and gain can be improved, the output stage is biased in class AB. The whole circuit is simulated with BSIM3V3 Spice model in HSpice based on TSMC 0.18μm. HSpice simulation shows that this structure has a significantly lower power consumption,compared to the traditional architectures, while maintaining almost the same gain,bandwidth and other key performances. At present, this amplifier has already been applied to 14 b/s ∑-△ A/D.
出处
《现代电子技术》
2007年第24期191-193,196,共4页
Modern Electronics Technique
基金
西安应用材料创新基金资助项目(XA-AM-200503)
