摘要
采用40 nm CMOS工艺设计了一款12位200 ksample/s低功耗数模转换器(DAC)芯片。结合建立速度和静态性能的设计指标,设计了“7+5”分段式电压与电流组合型结构和AB类输出缓冲器,在保证建立速度的条件下考虑到电阻的失配性,实现了良好的微分非线性(DNL)和积分非线性(INL)特性。测试结果表明,在-40~125℃下,DNL<0.2 LSB,INL<2 LSB,DAC具有精度高、单调性好、负载能力强的特点。
A 12-bit 200 ksample/s low-power digital-to-analog converter(DAC)chip is designed using 40 nm CMOS process.Combining the design indicators of establishment speed and static performance,a"7+5"segmented voltage-current combination structure and a class-AB output buffer are designed.Considering the resistance mismatch while ensuring the establishment speed,good differential nonlinearity(DNL)and integral nonlinearity(INL)characteristics are achieved.The test results show that from-40℃to 125℃,DNL is less than 0.2 LSB and INL is less than 2 LSB.The proposed DAC has the characteristics of high accuracy,good monotonicity and strong load capability.
作者
桂伯正
黄嵩人
GUI Bozheng;HUANG Songren(School of Physics and Optoelectronic Engineering,Xiangtan University,Xiangtan 411105,China)
出处
《电子与封装》
2025年第2期39-43,共5页
Electronics & Packaging
关键词
数模转换器
微分非线性
积分非线性
AB类输出缓冲器
digital-to-analog converter
differential nonlinearity
integral nonlinearity
class-AB output buffer
