传统流水线CORDIC(Coordinate Rotation Digital Computer,CORDIC)算法精度不高,输出延时较大,并且需要依靠剩余角度计算进行旋转方向的判断,占用较大的资源。针对以上问题,本文采用角度二极化重编码方法消除剩余角度计算,通过折叠角度...传统流水线CORDIC(Coordinate Rotation Digital Computer,CORDIC)算法精度不高,输出延时较大,并且需要依靠剩余角度计算进行旋转方向的判断,占用较大的资源。针对以上问题,本文采用角度二极化重编码方法消除剩余角度计算,通过折叠角度区间将角度映射于区间[0,π/4]。结合查找表以及合并迭代技术,减少角度计算的迭代次数和硬件单元,降低输出时延,只需要3个周期就能完成CORDIC计算。使用结果重映射方法完成正弦和余弦的全象限实现。寄存器资源消耗为传统算法的35.37%,输出时延减少85%。基于180nm CMOS工艺,完成CORDIC算法的ASIC实现。正弦和余弦的平均绝对误差分别为2.5472×10^(-6)、1.9396×10^(-6),相比较于传统CORDIC算法,精度提升一个数量级。展开更多
The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approx...The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.展开更多
文摘传统流水线CORDIC(Coordinate Rotation Digital Computer,CORDIC)算法精度不高,输出延时较大,并且需要依靠剩余角度计算进行旋转方向的判断,占用较大的资源。针对以上问题,本文采用角度二极化重编码方法消除剩余角度计算,通过折叠角度区间将角度映射于区间[0,π/4]。结合查找表以及合并迭代技术,减少角度计算的迭代次数和硬件单元,降低输出时延,只需要3个周期就能完成CORDIC计算。使用结果重映射方法完成正弦和余弦的全象限实现。寄存器资源消耗为传统算法的35.37%,输出时延减少85%。基于180nm CMOS工艺,完成CORDIC算法的ASIC实现。正弦和余弦的平均绝对误差分别为2.5472×10^(-6)、1.9396×10^(-6),相比较于传统CORDIC算法,精度提升一个数量级。
基金support from Grant PID2020-116075GB-C21funded by MCIN/AEI/10.13039/501100011033+1 种基金by“ERDF A way of making Europe”under Grant PID2020-116075GB-C21They also acknowledge financial support from the State Agency for Research of the Spanish Ministry of Science and Innovation through the“Unit of Excellence Maria de Maeztu 2020-2023”award to the Institute of Cosmos Sciences(CEX2019-000918-M)。
文摘The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.
