Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-sca...Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and展开更多
测试问题已成为SoC发展过程中的瓶颈,提出一种新的Wrapper扫描链平衡算法以期缩短IP核测试时间。算法首先计算Wrapper扫描链长度平均值,再结合特定的余量值,计算得到一个取值区间,记该区间为平均值余量;然后将IP核的内部扫描链按其长度...测试问题已成为SoC发展过程中的瓶颈,提出一种新的Wrapper扫描链平衡算法以期缩短IP核测试时间。算法首先计算Wrapper扫描链长度平均值,再结合特定的余量值,计算得到一个取值区间,记该区间为平均值余量;然后将IP核的内部扫描链按其长度降序排列,每次均将最长的内部扫描链添加到某条Wrapper扫描链上,直到该Wrapper扫描链长度在平均值余量所指定的区间内为止。以ITC'02 SoC Test Benchmarks内的所有测试集为对象完成的实验证明本算法能极其有效的通过扫描链平衡设计缩短IP核测试时间。展开更多
基于IP(intellectual property)核的系统级芯片的测试已成为SoC(system on chip)发展中的瓶颈,提出了一种采用BBO(biogeography based optimization)算法的Wrapper扫描链设计方法,使得Wrapper扫描链均衡化,从而达到IP核测试时间最小化...基于IP(intellectual property)核的系统级芯片的测试已成为SoC(system on chip)发展中的瓶颈,提出了一种采用BBO(biogeography based optimization)算法的Wrapper扫描链设计方法,使得Wrapper扫描链均衡化,从而达到IP核测试时间最小化的目的。本算法基于群体智能,通过实施迁徙操作和变异操作,实现Wrapper扫描链均衡化设计。本文以ITC'02 Test bench-marks中的典型IP核为实验对象,实验结果表明本算法相比BFD(best fit decrease)等算法,能够进一步缩短Wrapper扫描链,从而缩短IP核测试时间。展开更多
提出用于均衡Wrapper扫描链的交换优化算法以及用于测试调度的局部最优算法,这两种算法依据测试总线空闲率(IBPTB)指标,可从IP层和系统顶层对系统芯片(SOC)测试时间实现联合优化,进而使SOC的测试时间大大降低.为了验证两种算法及其联合...提出用于均衡Wrapper扫描链的交换优化算法以及用于测试调度的局部最优算法,这两种算法依据测试总线空闲率(IBPTB)指标,可从IP层和系统顶层对系统芯片(SOC)测试时间实现联合优化,进而使SOC的测试时间大大降低.为了验证两种算法及其联合优化性能的有效性和可靠性,对基于ITC’02国际SOC基准电路进行了相关的验证试验.针对p93791基准电路中core6 IP核,交换优化算法能得到比经典BFD(best fit decreasing)算法更均衡的Wrapper扫描链,在最佳情况下最长Wrapper扫描链长度减少2.6%;针对d695基准电路,局部最优算法根据IP核的IBPTB指标,可使相应SOC的测试时间在最优时比经典整数线性规划(ILP)算法减少12.7%.展开更多
基金This work was supported in part by the National Basic Research 973 Program of China under Grant No. 2011CB302503 and the National Natural Science Foundation of China under Grant Nos. 60806014, 61076037, 60906018, 61173006, 60921002, 60831160526.
文摘Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs. Thre dimensional （3D） integration has been proposed to sustain Moore＇s law by incorporating through-silicon vias （TSVs） to integrate different circuit modules in the vertical direction, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-on- Chips （SoCs）. Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. In addition, vertical interconnects, i.e., TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding pads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively. It is composed of two steps, i.e., scan chain allocation and functional input/output insertion, both of which can reduce TSV count significantly. Through extensive experimental evaluations, it is shown that reduce the number of test TSVs dramatically, i.e., as much as 26% in comparison with the intuitive method. the test wrapper chain structure designed by our method can 60.5% reductions in comparison with the random method and
文摘测试问题已成为SoC发展过程中的瓶颈,提出一种新的Wrapper扫描链平衡算法以期缩短IP核测试时间。算法首先计算Wrapper扫描链长度平均值,再结合特定的余量值,计算得到一个取值区间,记该区间为平均值余量;然后将IP核的内部扫描链按其长度降序排列,每次均将最长的内部扫描链添加到某条Wrapper扫描链上,直到该Wrapper扫描链长度在平均值余量所指定的区间内为止。以ITC'02 SoC Test Benchmarks内的所有测试集为对象完成的实验证明本算法能极其有效的通过扫描链平衡设计缩短IP核测试时间。
文摘基于IP(intellectual property)核的系统级芯片的测试已成为SoC(system on chip)发展中的瓶颈,提出了一种采用BBO(biogeography based optimization)算法的Wrapper扫描链设计方法,使得Wrapper扫描链均衡化,从而达到IP核测试时间最小化的目的。本算法基于群体智能,通过实施迁徙操作和变异操作,实现Wrapper扫描链均衡化设计。本文以ITC'02 Test bench-marks中的典型IP核为实验对象,实验结果表明本算法相比BFD(best fit decrease)等算法,能够进一步缩短Wrapper扫描链,从而缩短IP核测试时间。
文摘提出用于均衡Wrapper扫描链的交换优化算法以及用于测试调度的局部最优算法,这两种算法依据测试总线空闲率(IBPTB)指标,可从IP层和系统顶层对系统芯片(SOC)测试时间实现联合优化,进而使SOC的测试时间大大降低.为了验证两种算法及其联合优化性能的有效性和可靠性,对基于ITC’02国际SOC基准电路进行了相关的验证试验.针对p93791基准电路中core6 IP核,交换优化算法能得到比经典BFD(best fit decreasing)算法更均衡的Wrapper扫描链,在最佳情况下最长Wrapper扫描链长度减少2.6%;针对d695基准电路,局部最优算法根据IP核的IBPTB指标,可使相应SOC的测试时间在最优时比经典整数线性规划(ILP)算法减少12.7%.
