We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning...We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning results. Based on the critical path and the accumulated slack distances we define,we choose the best position for insertion and do a series of operations incrementally, such as deleting modules, adding modules, and resizing modules quickly. This incremental floorplanning algorithm has a very high speed less than 1μm,which is one of the most important measures in this research. The algorithm preserves the original good performances on area and wire length. It can also supply other tools with good physical estimates for area, wire length, and other performance guidelines.展开更多
The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extend...The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.展开更多
Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimat...Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.展开更多
Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed...Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed-outline floorplanning. This issue imposes fixed-outline constraints on the outline-free floorplanning, making the physical design more interesting and challenging. The contributions of this paper are primarily twofold. First, a modified simulated annealing(MSA) algorithm is proposed. In the beginning of the evolutionary process, a new attenuation formula is used to decrease the temperature slowly, to enhance MSA's global searching capacity. After a period of time, the traditional attenuation formula is employed to decrease the temperature rapidly, to maintain MSA's local searching capacity. Second, an excessive area model is designed to guide MSA to find feasible solutions readily. This can save much time for refining feasible solutions. Additionally, B*-tree representation is known as a very useful method for characterizing floorplanning. Therefore, it is employed to perform a perturbing operation for MSA. Finally, six groups of benchmark instances with different dead spaces and aspect ratios—circuits n10, n30, n50, n100, n200, and n300—are chosen to demonstrate the efficiency of our proposed method on fixed-outline floorplanning. Compared to several existing methods, the proposed method is more efficient in obtaining desirable objective function values associated with the chip area, wirelength, and fixed-outline constraints.展开更多
As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-syn...As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.展开更多
With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we prop...With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we propose a new method of handling rectilinear blocks. In this paper, the handling of the rectilinear blocks is simplified by transforming the L/T- shaped block problem into the Mign-abutment constraint problem. We devise the block rejoining process and block alignment operation for forming the L/T-shaped blocks into their original configurations. The shape flexibility of the soft blocks, and the rotation and reflection of L/T-shaped blocks are exploited to obtain a tight packing. The empty rooms are introduced to the process of block rejoining. The efficiency and effectiveness of the proposed method are demonstrated by the experimental results on a set of some benchmark examples.展开更多
This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. I...This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.展开更多
针对只有硬模块的布图规划问题,通常将其构建成组合优化模型,但求解过程时间成本高。为提高求解效率,提出了一种基于非光滑解析数学规划的布图规划算法。基于布图中器件的坐标表示,构建了一个泛化的非光滑解析数学规划模型,将不同场景...针对只有硬模块的布图规划问题,通常将其构建成组合优化模型,但求解过程时间成本高。为提高求解效率,提出了一种基于非光滑解析数学规划的布图规划算法。基于布图中器件的坐标表示,构建了一个泛化的非光滑解析数学规划模型,将不同场景下的布图规划问题的不同优化阶段处理为该泛化模型的特例,并利用共轭次梯度算法(conjugate sub-gradient algorithm,CSA)对其进行求解。针对固定轮廓布图规划问题,通过统一框架下的全局布图规划、合法化、局部优化三个阶段,实现了在固定轮廓约束下的线长优化。针对无固定轮廓约束问题,提出了带黄金分割策略的共轭次梯度算法(conjugate sub-gradient algorithm with golden section strategy,CSA_GSS),利用黄金分割策略缩小固定轮廓的面积,达到面积和线长双优化的效果。实验在GSRC测试电路上与基于B*-树表示的布图规划算法进行比较,该算法对于大规模电路在线长和时间方面均占据优势。实验结果表明,该算法能以更低的时间复杂度获得更优的线长。展开更多
文摘We present a novel incremental algorithm for non-slicing floorplans based on the corner block list representation. The horizontal and vertical adjacency graphs are derived from the packing of the initial floorplanning results. Based on the critical path and the accumulated slack distances we define,we choose the best position for insertion and do a series of operations incrementally, such as deleting modules, adding modules, and resizing modules quickly. This incremental floorplanning algorithm has a very high speed less than 1μm,which is one of the most important measures in this research. The algorithm preserves the original good performances on area and wire length. It can also supply other tools with good physical estimates for area, wire length, and other performance guidelines.
文摘The Gauss-Seidel method is effective to solve the traditional sparse linear system. In the paper, we define a class of sparse linear systems in iterative algorithm. The iterative method for linear system can be extended to the dummy sparse linear system. We apply the Gauss-Seidel method, which is one of the iterative methods for linear system, to the thermal model of floorplan of VLSI physical design. The experimental results of dummy sparse linear system are computed by using Gauss-Seidel method that have shown our theory analysis and extendibility. The iterative time of our incremental thermal model is 5 times faster than that of the inverting matrix method.
文摘Floorplanning is a prominent area in the Very Large-Scale Integrated (VLSI) circuit design automation, because it influences the performance, size, yield and reliability of the VLSI chips. It is the process of estimating the positions and shapes of the modules. A high packing density, small feature size and high clock frequency make the Integrated Circuit (IC) to dissipate large amount of heat. So, in this paper, a methodology is presented to distribute the temperature of the module on the layout while simultaneously optimizing the total area and wirelength by using a hybrid Particle Swarm Optimization-Harmony Search (HPSOHS) algorithm. This hybrid algorithm employs diversification technique (PSO) to obtain global optima and intensification strategy (HS) to achieve the best solution at the local level and Modified Corner List algorithm (MCL) for floorplan representation. A thermal modelling tool called hotspot tool is integrated with the proposed algorithm to obtain the temperature at the block level. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results obtained are compared with the solutions derived from other stochastic algorithms and the proposed algorithm provides better solution.
基金supported by the National Natural Science Foundation of China(Nos.61403174 and 61503165)the Natural Science Foundation of the Jiangsu Higher Education Institutions of China(No.14KJB 520011)the Jiangsu Provincial Science Foundation for Youths(No.BK20150239)
文摘Outline-free floorplanning focuses on area and wirelength reductions, which are usually meaningless, since they can hardly satisfy modern design requirements. We concentrate on a more difficult and useful issue, fixed-outline floorplanning. This issue imposes fixed-outline constraints on the outline-free floorplanning, making the physical design more interesting and challenging. The contributions of this paper are primarily twofold. First, a modified simulated annealing(MSA) algorithm is proposed. In the beginning of the evolutionary process, a new attenuation formula is used to decrease the temperature slowly, to enhance MSA's global searching capacity. After a period of time, the traditional attenuation formula is employed to decrease the temperature rapidly, to maintain MSA's local searching capacity. Second, an excessive area model is designed to guide MSA to find feasible solutions readily. This can save much time for refining feasible solutions. Additionally, B*-tree representation is known as a very useful method for characterizing floorplanning. Therefore, it is employed to perform a perturbing operation for MSA. Finally, six groups of benchmark instances with different dead spaces and aspect ratios—circuits n10, n30, n50, n100, n200, and n300—are chosen to demonstrate the efficiency of our proposed method on fixed-outline floorplanning. Compared to several existing methods, the proposed method is more efficient in obtaining desirable objective function values associated with the chip area, wirelength, and fixed-outline constraints.
基金the National Natural Science Foundation of China (Nos. 90407005, 90207017, 60236020, and 60121120706)
文摘As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.
基金This work is supported by the National Natural Science Foundation of China （Grant Nos. 60473126 and 90407005）, National Natural Science Foundation of China and Hong Kong RGC Joint Project （Grant No. 60218004） and the Hi-Tech Research ＆ Development 863 Program of China （Grant Nos. 2004AA1Z1050 and 2002AA1Z1460）.
文摘With the recent advent of deep submicron technology and new packing schemes, the components in the integrated circuit are often not rectangular. On the basis of the representation of Corner Block List （CBL）, we propose a new method of handling rectilinear blocks. In this paper, the handling of the rectilinear blocks is simplified by transforming the L/T- shaped block problem into the Mign-abutment constraint problem. We devise the block rejoining process and block alignment operation for forming the L/T-shaped blocks into their original configurations. The shape flexibility of the soft blocks, and the rotation and reflection of L/T-shaped blocks are exploited to obtain a tight packing. The empty rooms are introduced to the process of block rejoining. The efficiency and effectiveness of the proposed method are demonstrated by the experimental results on a set of some benchmark examples.
文摘This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.
文摘针对只有硬模块的布图规划问题,通常将其构建成组合优化模型,但求解过程时间成本高。为提高求解效率,提出了一种基于非光滑解析数学规划的布图规划算法。基于布图中器件的坐标表示,构建了一个泛化的非光滑解析数学规划模型,将不同场景下的布图规划问题的不同优化阶段处理为该泛化模型的特例,并利用共轭次梯度算法(conjugate sub-gradient algorithm,CSA)对其进行求解。针对固定轮廓布图规划问题,通过统一框架下的全局布图规划、合法化、局部优化三个阶段,实现了在固定轮廓约束下的线长优化。针对无固定轮廓约束问题,提出了带黄金分割策略的共轭次梯度算法(conjugate sub-gradient algorithm with golden section strategy,CSA_GSS),利用黄金分割策略缩小固定轮廓的面积,达到面积和线长双优化的效果。实验在GSRC测试电路上与基于B*-树表示的布图规划算法进行比较,该算法对于大规模电路在线长和时间方面均占据优势。实验结果表明,该算法能以更低的时间复杂度获得更优的线长。
