摘要
随着重用方法学被引入到超大规模集成电路设计中,宏单元的使用率大幅提高。宏单元与标准单元之间巨大的尺寸差异给电路布局器带来了严峻的挑战。该文提出并实现了基于张力微调和线长驱动的宏单元布局器WIMPlace。该文方法结合了基于权重的分割方法和受液体表面张力原理启发的宏单元微调技术,以实现有效的宏放置。WIMPlace算法采用4步流程:预处理、预布局、宏微调和宏合法化,并在其中宏微调阶段合理利用标准单元密度和线长函数进行优化。该文采用DREAMPlace2.0布局工具作为后端布局器,并在现代混合尺寸(MMS)测试集上进行实验。实验结果表明,与学术界领先的混合尺寸布局器ePlace-MS和最新的DREAMPlace4.0结果相比,在总共16个案例中的15个中,该文所提的WIMPlace算法都实现了最短的线长(HPWL),这表明该文方法在优化线长方面非常有效。
Objective With the introduction of reuse methodologies in integrated circuit design,the utilization of macro cells in Very Large Scale Integration(VLSI)has significantly increased.However,the considerable size difference between macro cells and standard cells presents a significant challenge for circuit placers.This study proposes a novel macro placer,WIMPlace,based on tension fine-tuning and wirelength-driven approaches.The aim is to address issues such as density imbalance and degradation of solution quality observed in existing mixed-size placers,thereby providing a more effective solution for VLSI design.Methods The proposed method in this paper consists of four stages:preprocessing,pre-placement,macro cell fine-tuning,and macro legalization.Initially,a weight-based partitioning approach is employed to group standard cells with macro into supersets,addressing density issues during the initial placement(Section 3.1).In the pre-placement stage,the DREAMPlace 2.0 tool is used for placing standard cells,and the initial positions of macro cells are determined based on the locations of these clusters(Section 3.2).A local tension model,inspired by the principle of surface tension in liquids,is then adopted to fine-tune the positions of macros,ensuring that connections between standard cells and macros are as compact as possible(Section 3.3,Fig.2).Finally,a constraint graph-based macro legalization strategy is applied to prevent overlaps between macros(Section 3.4,Fig.3).Results and Discussions Experimental results demonstrate that the WIMPlace achieves exceptional performance on the MMS benchmark,outperforming other advanced mixed-size placers,such as ePlace-MS and DREAMPlace 4.0.Specifically,in 15 out of 16 cases,it achieved the shortest wirelength,with average reductions of 4.31%and 2.39%,respectively(Section 4,Table 2).Additionally,WIMPlace exhibits excellent solution stability,particularly showing a linear increase in runtime as the number of cells increases(Section 4,Fig.4),indicating that the algorithm not only optimizes wirelength effectively but also demonstrates high computational efficiency.Notably,in the newblue3 case,despite the macro cells occupying a significant portion of the chip area,WIMPlace still demonstrated strong adaptability.Conclusions In summary,WIMPlace,as proposed in this paper,is an efficient macro cell placer that achieves gradual fine-tuning optimization of macro cells by combining gradient field movements based on a surface tension analogy and employing preprocessing techniques to balance macros with their associated standard cells.Compared to existing mixed-size placers,WIMPlace demonstrates superior performance across multiple key metrics,particularly in wirelength optimization.Future work could focus on integrating additional design objectives,such as timing,congestion,and thermal management,to enhance the applicability and flexibility of WIMPlace.This study provides new perspectives and technical approaches for VLSI design.
作者
朱彦臻
严浩鹏
蔡述庭
高鹏
ZHU Yanzhen;YAN Haopeng;CAI Shuting;GAO Peng(School of Integrated Circuits,Guangdong University of Technology,Guangzhou 510006,China)
出处
《电子与信息学报》
北大核心
2025年第7期2396-2404,共9页
Journal of Electronics & Information Technology
基金
广东省科技计划(2022B0701180001)。
关键词
超大规模集成电路
布图规划
宏布局
混合尺寸布局
迭代布局
Very Large Scale Integration(VLSI)
Floorplan
Macro placement
Mixed-size placement
Iterative placement
