摘要
介绍了一种用于接收1.25Gbit/s不归零随机数据的吉比特以太网接收器的设计。该电路采用半速率时钟结构,目的是为了以较低的功耗和简单的结构适应高速数据流。本文介绍了电路的主要组成部分和工作原理,突出了关键模块的设计。电路采用1.8V 0.18祄 1P6M CMOS工艺,经SpectreS仿真验证以及流片测试,主要功能已经实现。
An Ethernet receiver for 1.25Gbit/s NRZ data is described. This circuit works at half of the data rate, in order to be adapted with high rate data stream with low power and reduced complexity for design. The main building blocks and operation principles are introduced, and the key parts of the circuit are also described. The circuit adopts 1.8V 0.18祄 CMOS 1P6M technology. Verified with SpectreS simulator, the circuit works properly under different corners. The chip is tested, and the main function is correct.
出处
《通信学报》
EI
CSCD
北大核心
2004年第5期101-108,共8页
Journal on Communications
