摘要
采用二相埋沟结构,研制成了2×455位高速 CCD 模拟延迟线,其动态范围达到46dB,时钟频率超过10MHz。本文详细地叙述器件设计,并对器件的主要参数进行分析讨论。
A 2×455 bit high speed CCD analog delay line has been developed with towphase buried channel architecture which dynamic range is 46 dB and clock frequency over 10MHz.In this paper, the design considerations of the device are de- scribed in detail.Analysis and discussion are made on the principal parameters.
出处
《半导体光电》
CAS
CSCD
北大核心
1993年第2期138-141,147,共5页
Semiconductor Optoelectronics
关键词
模拟延迟线
时钟频率
延时线
Analog Delay Line
Clock Frequency
Dynamic Range
