摘要
采用四相埋沟结沟制作了器件,其转移效率超过99.99%,时钟频率超过10MHz。本文阐述了器件原理、结构和工艺以及提高器件参数的重要途径。
A 283(1/2) bit BCCD analog delay line whose transfer efficiency is over 99.99% and clock frequency over 10 MHz has been fabricated with four-phase buried struclute.The principle,configuration and technology of the device are des- cribed as weIl as an important approach to the impmovement of the device parameters.
出处
《半导体光电》
CAS
CSCD
北大核心
1990年第3期210-215,共6页
Semiconductor Optoelectronics
关键词
BCCD
模拟
延迟线
结构
工艺
Analog Delay Line
Configuration and Process
