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50V/40mΩVDMOSFET单胞尺寸的最佳设计 被引量:1

The Cell-size Optimum Design Of VDMOSFET(50V/40mΩ)
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摘要 本文以正方形单胞为例 ,较系统地分析了器件的物理机制、结构及其工作原理 ,并通过大量计算和分析找出多晶硅窗口区尺寸 LW和多晶硅尺寸 LP的最佳设计比例 ,阐述了器件的最佳化设计思想。通过具体给定的参数确定了外延层电阻率及外延层厚度、运用迭代法算出栅氧化物厚度 TOX、P区扩散浓度 NP。然后由最佳 LW和 LP值给出相应的特征导通电阻 Ron。进而给出有效面积和单胞数。 This paper analyzes the physical machine,device struction and working principle systematically for the square cell.Throughamount of calculation,we give the best proportion of window width (L W) and polysilicon width (L P),and give the method of optimum design.This paper works out the thickness and resistivity of the epitaxial layer under the giver parameters,gives the thickness (T ox) of the gate and the density of P diffusion part (N P) adopting the iteration method.Specifically,the specific on-resistance is conducted based on the proper value pair of L W and L P.The efficient area and the number of cell are given at last.
作者 闫冬梅 张雯
出处 《微处理机》 2004年第2期5-7,共3页 Microprocessors
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参考文献5

  • 1[1]Krishna Shenai,Charles S.Korman.A50-V,0.7-m Ω·cm2,Vertical-Power DMOSFET[J].IEEE ElectronL Devic Letters,1989;10(3):101-103.
  • 2[2]Krishna Shenai.Optimally Scaled Low-Voltage Vertical Power MOSFET's for High-Frequency Power Conversion[J].IEEE Transactions On Electron Devices,1990;37(4):1141-1151.
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  • 4[4]Kevin J.Fischer,Krishna Shenai.Effect of Bipolar Turn-On on the Static Current-Voltage Characteristics of Scaled Vertical Power DMOSFET's[J].IEEE Transactions On Electron Devices,1995;42(3):555-563.
  • 5[5]J Rebollo,E Figueras,et al.ANALYSIS OF THE QUASI-SATURATION REGION OF HIGH VOLTAGE VDMOS DEVICES[J].Solid-State Electronics,1987;30(2):177-180.

同被引文献4

  • 1R G Wangner, J Soden, C F Hawkins. Extent and cost of EOS/ESD damage in an IC manufacturing process[C].In. Proc. 15th EOS/ESD Symposium, 1993.49-55.
  • 2李泽宏,易黎,张磊.多晶硅ESD结构保护的垂直双扩散金属氧化物半导体功率器件,中国专利,200610022264.2[P].2007-5-16.
  • 3朱袁正,秦旭光.一种深沟槽大功率MOS器件及其制造方法,中国专利.200710302461.4[P].2008.7-2.
  • 4王蓉,李德昌.低压功率VDMOS的结构设计研究[J].电子科技,2010,23(4):33-35. 被引量:2

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