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一种抗差分功耗攻击的改进DES算法及其硬件实现 被引量:20

Advanced DES Algorithm Against Differential Power Analysis and Its Hardware Implementation
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摘要 该文在研究差分功耗分析 (differentialpoweranalysis,DPA)模型的基础上 ,同时考虑DES算法的特点以及存储空间的局限性 ,提出了把MASK技术应用于DES算法线性部分的抗DPA攻击的改进DES算法 ,即DES-DPA算法 ,并以此为基础设计了防止DPA攻击的DES-DPA模块 .此外从差分功耗攻击的原理上简要说明DES-DPA算法能够有效地防止功耗分析 .结果表明在基于 0 .2 5 μm标准单元库工艺下 ,DES-DPA模块的综合规模为 1 91 4门 ,最大延时为 9.5 7ns,可以工作于 1 0 0MHz左右的频率下 ,各项性能指标均能满足智能卡和信息安全系统的要求 . The advanced DES_DPA algorithm different from differential power analysis (DPA) is provided based on the original model of DPA. The DES_DPA module is built according to the above principle, which the linear part of the module adopt the MASK technology for the specialty of the DES algorithm and the localizations of the storage. And its efficiency is explained from the view of DPA's principle. With 0.25 μm CMOS technology library, the result shows that the gate count of DES_DPA module is about 1914, the maximal delay is 9.57 ns, and can be worked correctly under 100 MHz, so that it is well suited to the field of smart card and the information security.
出处 《计算机学报》 EI CSCD 北大核心 2004年第3期334-338,共5页 Chinese Journal of Computers
关键词 DES算法 硬件 信息安全 密码体制 差分功耗分析 Algorithms Delay circuits Differential amplifiers Hardware Signal to noise ratio
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参考文献9

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