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现代半导体研制的内建可靠性方法 被引量:3

The Build-In Reliability (BIR) System for Advanced Semiconductor Manufacturing
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摘要 为满足半导体技术的高速发展与进步的要求以及客户对产品的性能、服务、运送、质量及可靠性等方面的期望,我们有必要尽早地把有缺陷的产品从生产线上鉴别出来,并采用更为有效的方法来开发、验证及监控工艺过程。传统的测试式可靠性方法,主要在生产线末端通过老化、品质管理、可靠性测试和失效分析等手段来鉴别或评估可靠性失效率,由于其测试周期长,已不再适用于现代半导体工业。内建可靠性方法正好相反,它具有迅速反馈、早期预警和循环控制等优点。对半导体制造业来说,内建可靠性方法由两大部分组成:圆片级可靠性系统和内建可靠性数据库。我们已经成功地运用此方法完成了从0.35~0.13μm技术的产品可靠性认证和工艺监控。 To cope with the fast advancement and rapid evolution of the semiconductor technologies and customers' expectations toward better performance, service, delivery, quality, and reliability, producers need to identify defects earlier in the production lines and to develop, qualify, and monitor processes in more effective and efficient manners. This makes the conventional test-in reliability (TIR) approach, which heavily relies on burn-in, qualification, reliability tests, and failure analysis activities at the end of manufacturing line to screen or measure reliability failure rate, unsuitable for the modern semiconductor industries due to the long cycle time. The build-in reliability (BIR) methodology, on the contrary, preserves the merits of fast response, early alarm, and closed-loop control. The BIR manufacturing framework consists of two major systems: wafer- level reliability (WLR) and the BIR database . We successfully apply the BIR methodology to qualify and monitor technologies from 0.35um to 0.13um.
出处 《电子产品可靠性与环境试验》 2003年第6期13-20,共8页 Electronic Product Reliability and Environmental Testing
关键词 内建可靠性 测试式可靠性 半导体 圆片级可靠性 BIR TIR semiconductor WLR
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参考文献5

  • 1Kary Chien W T, Chiang Shunwang, Tseng Summer F C,et al. Practical WLRC Methodology & Applications in A Wafer Foundry [A] . International Reliability Physics Symposium [C] . Dallas: Tx, 2003.
  • 2Chien W T Kary, Huang Charles H J. Practical BuildingIn Reliability (BIR) Approaches for Semiconductor Manufacturing [J] . IEEE Transactions on Reliability, 2002, 51(4) : 469-481.
  • 3Way Kuo, Wei-Ting Kary Chien, Taeho Kim. Reliability,Yield, and Stress Burn-In - A Unified Approach for Microelectronics Systems Manufacturing and Software Developmenf, [M] Boston: Kluwar Science, 1998.
  • 4McPherson J W. Does Building-In Reliability Imply More or Less Wafer-Level Reliability Testing? [A] . International Integrated Reliability Workshop Final Report [C] .1996. 1-15.
  • 5Erhart D H, Schafft H A, Gladden W K. On the Road to Building-In Reliability [A] . International Integrated Re liability Workshop Final Report [C] . 1995.5-10.

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