摘要
用ETCO算法对SRAM进行了内建自测试设计.首先说明了设计的原理,进而对电路中所用的各个单元电路进行了设计,主要包括地址计数器、数据计数器和BIST控制器等.设计出的电路可针对具体的故障模型设置相应的测试长度,从而获得预期的故障覆盖率.测试时不需存储正确响应,并可通过一个响应标志位表示检测的结果.可测性部分对电路硬件的开销较小,所设计的电路在工作站上已成功通过仿真,此电路可广泛应用于嵌入式SRAM,以降低电路的测试难度.
This paper proposed a kind of design for memory arrays with built-in self-test (BIST).We first introduced the design principle, and then described the design for all the cell circuits, which include the address counters, data generators, and BIST controller. The design has the following characteristics:① The test length can be changed to get the desired fault coverage of any kind of fault models; ② The correct response is not necessary to be stored; ③ A single response bit always indicates whether there is a fault;④ The hardware overhead is low. The simulation result shows its correctness.
出处
《湖南大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2003年第6期22-25,共4页
Journal of Hunan University:Natural Sciences
关键词
内建自测试
线性反馈移位寄存器
故障覆盖率
本原多项式
built-in self-test
Linear-feedback Shift Register (LFSR)
fault coverage
primitive polynomial
