摘要
FIR滤波器是一种被广泛应用的基本的数字信号处理部件。针对采用常用的软、硬件方法设计实现FIR滤波器存在的问题 ,提出采用MATLAB的窗函数方法设计并在FPGA上高效实现严格线性相位FIR滤波器的方案。通过编程调试得到满意的结果。该方法实现FIR滤波器器件体积小、性能可靠、价格低廉、设计周期短 ,可作为高速数字滤波设计的较好方案。
FIR filer is a basic processing unit for digital signal in common use . This paper aimed at the problems that the FIR filer is implemented using software and hardware designing methods, and presented a scheme which is designed with a FIR filer of high linear phase and can be effectively realized in FPGA. The satisfying results were gained through programming and debugging for the design. The FIR filer implemented with the scheme is a smaller volume, high reliability, lower cost, and shorter designing time. Therefore, it is a better scheme for designing high speed digital filer.
出处
《计算机仿真》
CSCD
2003年第12期144-146,共3页
Computer Simulation
