摘要
给出了基于 0 .2 um Ga As PHEMT工艺的 10 GHz单片频率综合器的系统模型、电路结构、性能分析、版图设计以及仿真结果 ,并简单介绍了工艺特点。整个芯片由压控振荡器、分频器、鉴相器以及低通滤波器组成。在 ADS软件下的仿真结果表明 :芯片采用 3 .3 V单电源供电 ,总功耗为 40 0 m W,输出功率为 -15 d Bm,工作频率 9.5 GHz～ 11.0 GHz,相位噪声 -95 d Bc/Hz@1MHz,输出信号的峰峰值抖动约为 2 ps。整个芯片面积为 1.2 5× 1.3 5 mm2 。
This paper presents the design and characterization of a monolithic 10GHz frequency synthesizer/multiplier based on a 0.2μm GaAs PHEMT technology. They include system model, circuits topology, performance analyse, layout design, simulation results and process characteristic. The chip is composed of a VCO, a frequency divider, a phase detector and a low pass filter. The simulation results in ADS show that: The power consumption is 400 mW at supply voltage of 3.3V. The output power is about -15dBm. The operating frequency range covers 9.5GHz^11.0GHz. The phase noise is -95dBc/Hz@1MHz and peak to peak jitter is about 2ps. The chip size is 1 25×1 35mm 2. It can be adopted in the clock generating circuits of 10 Gigabit Ethernet.
出处
《电气电子教学学报》
2003年第6期36-39,共4页
Journal of Electrical and Electronic Education
