摘要
根据字串行算法,使用字串行加法器、字串行乘法器和延时器基本功能模块,构建了一种基于FPGA的字串行FIR滤波器.与传统的位串行方式相比,构建的字串行FIR滤波器提高了运行速度,减少了硬件消耗,可更好的协调速度与占用面积的关系.并通过几种5阶FIR滤波器实现性能的比较,得出字长N=2的字串行FIR滤波器具有最小的面积—时间积.
The implementation of a digit_serial fir filter based on FAGA was proposed. According to digit_serial arithmetic, the digit_serial FIR filter was designed with the foundational function modules that included digit_serial adder, digit_serial multiplier and delay circuit. Compared with the traditional bit_serial method, the response speed of this digit_serial FIR filters has been improved and the hardware consumption has been decreased. At the same time, the relationship between speed and area could be adjusted in a better manner. And through the comparison of performance for several 5_tap FIR filter, it can be concluded that the digit_serial FIR filters with N=2 have the minimum area_time product.
出处
《北方交通大学学报》
CSCD
北大核心
2003年第6期48-51,共4页
Journal of Northern Jiaotong University
关键词
信息处理技术
现场可编程门阵列
字串行
位串行
FIR滤波器
information process technology
Field Programmable Gate Array(FPGA)
digit-serial
bit-serial
Finite Impulse Response(FIR) filters
