摘要
本文提出一种规整结构超前进位加法器,其加法时间与位数的对数成比例;而且其结构规整、逻辑简单、互连容易。SPICE模拟表明,采用2μm CMOS工艺的16位加法器最坏情况延时为5.4ns,并具有位数加倍延时仅增加1.2ns的扩展特性。它可以方便地用全定制或半定制等VLSI设计方法实现。
A regular carry look-ahead adder is presented in this paper. It gains very short delay proportional to logarithm of the bandwidth of the adder, regular architecture, simple logic and localized in-terconnectivity. SPICE simulation results show that for a 16-bit RCLA employing 2UUUUUUUUUm CMOS technology the addition time is 5.4ns in the worst case, and doubling the bandwidth only takes 1.2ns more delay. It can conveniently be implemented by various VLSI design styles, e. g. full-custom, cell based or gate array.
出处
《电子学报》
EI
CAS
CSCD
北大核心
1992年第2期83-86,共4页
Acta Electronica Sinica
基金
国家自然科学基金委员会资助。
