摘要
通用串行总线(USB)作为一种崭新的微机总线接口规范,具有即插即用、扩展方便等优点,已成为计算机必备的一个接口。采用VerilogHDL语言设计USBIPCore,分析时序设计要点。实现对主机发送的标准设备请求,返回设备描述符、传送数据等操作,并在MaxplusⅡ环境下进行了波形仿真和时序分析。时序仿真满足设计要求。
Universal Serial Bus (USB) is a brand-new computer bus protocol; it has the advantages of plug-and-play function and is eas y to be extent. USB has been a necessary bus in a computer. An exam ple about how to design USB control function IP Core is given to in troduce the process of designing IP Core based on Verilog HDL. At the same time, the main points in the design are outlined. The project c an send the Standard Device Requests, receive Standard Configuration Des criptor and transmit data ect. Waveform simulation and time analysis ar e finished in Maxplus Ⅱ.
出处
《莆田学院学报》
2002年第3期48-52,共5页
Journal of putian University
基金
华侨大学科研基金项目
